Field-Programmable Gate Arrays

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sytemverilog supported by quartus 6.0?

the systemverilog is a power tools used in verification,i want to learn it.
0 comments posted 20yrs
posted by cppcpldfpga
0 comments posted 20yrs posted by cppcpldfpga

state machine dead problem

I am having a very stange problem with my state machine. The state machine turns dead after some uncertain time(20min ~...
9 comments posted 20yrs
posted by Lathi.Tan
9 comments posted 20yrs posted by Lathi.Tan

Looking for ispMACH4000 eval boards

The board that Lattice sells come with virtually no docs, so I don't even consider that a product. I found one from a E...
1 comments posted 20yrs
posted by gnuarm
1 comments posted 20yrs posted by gnuarm

Translate fails in ISE 8.1

If I try to run the 'Implement Design' process in my project, the ISE errors out immediately. There is NO message in th...
3 comments posted 20yrs
posted by mottoblatto
3 comments posted 20yrs posted by mottoblatto

Virtex-4 BSCAN

The Virtex-4 data sheet states that the BSCAN module can support 4 user-data registers. However there is an Errata shee...
2 comments posted 20yrs
posted by davebXXX
2 comments posted 20yrs posted by davebXXX

Really slow programming time

Hi, I'm trying to program a prom on an Avnet development board for a Virtex4 FPGA using iMPACT. Load up the mcs file ok...
0 comments posted 20yrs
posted by ben.s.vaughan
0 comments posted 20yrs posted by ben.s.vaughan

I2C slaves needed

Hi, I need some (2 to 3) different I2C Slave models from different companies (in verilog) to test my I2C Bus .I have ve...
2 comments posted 20yrs
posted by vittal.patil
2 comments posted 20yrs posted by vittal.patil

Help required regarding PCI Master core

Hello experts, I am a final year student and working on my senior design project. I need PCI Master core and unfortunat...
16 comments posted 20yrs
posted by madnan.rashid
16 comments posted 20yrs posted by madnan.rashid

Generating Core component

Hello , I was wondering if anyone has any ideas on how I would got about generating a core. I've currently having a pro...
0 comments posted 20yrs
posted by luca_grossi
0 comments posted 20yrs posted by luca_grossi

CAN YOU SEE MY MESSAGE?

HELLO THERE CAN ANYBODY SEE MY MESSAGES? WHY ARENT THEY GETTING POSTED??????????????????????????????????????????????????...
7 comments posted 20yrs
posted by alexandre.aoun
7 comments posted 20yrs posted by alexandre.aoun

Aurora UCF problem

I'm having trouble getting some lines in a UCF file to be accepted by ISE. The lines are: NET Inst_rio_fo2_top/aurora_m...
3 comments posted 20yrs
posted by enquiries
3 comments posted 20yrs posted by enquiries

Spartan 3 or 3E ?

OK, I've read the xilinx blurb but I still don't understand the difference between 3 and 3E. If I have enough gates and...
2 comments posted 20yrs
posted by dave.garnett
2 comments posted 20yrs posted by dave.garnett

Balanced inputs on Spartan3E

I've come to FPGAs from CPLDs and am rapidly realising that a reasonable (but not complete) knowledge of Verilog is not...
1 comments posted 20yrs
posted by ethel.thefrog
1 comments posted 20yrs posted by ethel.thefrog