The Virtex-4 data sheet states that the BSCAN module can support 4 user-data registers.
However there is an Errata sheet which states that early (ES) parts only supported one register.
The "Virtex-4 Libraries Guide for HDL Designs" shows a BSCAN_VIRTEX4 element supporting only one user register (although it mentions USER1 & USER2 instructions, suggesting two registers).
The library unisim_VCOMP.vhd shows:
component BSCAN_VIRTEX -- This drives two user registers port ( DRCK1 : out std_ulogic := 'H'; DRCK2 : out std_ulogic := 'H'; RESET : out std_ulogic := 'H'; SEL1 : out std_ulogic := 'L'; SEL2 : out std_ulogic := 'L'; SHIFT : out std_ulogic := 'L'; TDI : out std_ulogic := 'L'; UPDATE : out std_ulogic := 'L'; TDO1 : in std_ulogic := 'X'; TDO2 : in std_ulogic := 'X' ); end component;
component BSCAN_VIRTEX4 -- This drives one user register generic ( JTAG_CHAIN : integer := 1 ); port ( CAPTURE : out std_ulogic := 'H'; DRCK : out std_ulogic := 'H'; RESET : out std_ulogic := 'H'; SEL : out std_ulogic := 'L'; SHIFT : out std_ulogic := 'L'; TDI : out std_ulogic := 'L'; UPDATE : out std_ulogic := 'L'; TDO : in std_ulogic := 'X' ); end component;
So I am confused :) Can anyone tell me just how many JTAG user registers V4 does support?