Field-Programmable Gate Arrays

PLB-IPIF and user IP interface problem

I have a problem in initiating a PLB _IPIF back to back transactions. I have integrated my IP backend with PLB-IPIF. My...

2 comments posted 19yrs

posted by ashish.shringarpure

2 comments posted 19yrs posted by ashish.shringarpure

lwip

hi i have a quick question: do i have to use lwip_init() for raw_api mode as well or do i have to call all the mem_init...

4 comments posted 19yrs

posted by u_stadler

4 comments posted 19yrs posted by u_stadler

ML501 where to order

Xilinx webshop related again I am ready to immediatly order ML501, but unfortunatly Xilinx website has only documentati...

3 comments posted 19yrs

posted by Antti.Lukats

3 comments posted 19yrs posted by Antti.Lukats

Configuration of Spartan 3 devices

Hello, I am considering to use Spartan 3 devices on our new board. Xilinx recommends XCF04S and XCF08P devices for conf...

14 comments posted 19yrs

posted by Karel.Deprez

14 comments posted 19yrs posted by Karel.Deprez

BSD Indi FPGA processor seeks new webserver

hi having difficulty doing a ftp logon need new ad free webserver space 50MB (no budget) any offers?? http://indi.joox.n...

1 comments posted 19yrs

posted by jackokring

1 comments posted 19yrs posted by jackokring

uBlaze prototype PCB UART issues

Hello all, Forgive me in advance for the long plea for help. Would anyone be kind enough to troubleshoot my implementat...

6 comments posted 19yrs

posted by fbs.consulting

6 comments posted 19yrs posted by fbs.consulting

Pack registers (from submodule) into IOB for bidirectionnal signal

Hello, I know that this has been discussed here a few times but I still can't find a definitive answer so here we go ag...

7 comments posted 19yrs

posted by prdubois

7 comments posted 19yrs posted by prdubois

Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1

Hi group This must sound like a dumb question. How can I update from ISE and EDK 8.1 to 8.2? I downlaoded and installed...

6 comments posted 19yrs

posted by m.zingg

6 comments posted 19yrs posted by m.zingg

PUBLISHABLE PAPER RELATED TO FPGA!

I am searching for a new topic related to FPGAs and that is publishable? Any ideas? I was thinking of area, performance...

25 comments posted 19yrs

posted by alexandre.aoun

25 comments posted 19yrs posted by alexandre.aoun

ise 8.2 partitions

does anybody uses partitions in Xilinx tools by command line? It seem they are available only in project navigator or i...

1 comments posted 19yrs

posted by bergnoli

1 comments posted 19yrs posted by bergnoli

ix/xxvi Puns

Barbar-Rick: What for a rich race. Premaining king: An ocean. Ting: A nitpickings.

0 comments posted 19yrs

posted by bt

0 comments posted 19yrs posted by bt

LCD(STN) controller

Hi I'm making a design in a FPGA for a colour STN LCD. The display is up and running in the 8 basic colours , RGB. We w...

1 comments posted 19yrs

posted by fredrik.karlsson

1 comments posted 19yrs posted by fredrik.karlsson

Migration from Spartan-2E to Spartan-3E

Hi, I'm investigating the possibility to replace an Spartan-2E (xc2s400e) with an Spartan-3E (xc3s1200e) device on a PC...

4 comments posted 19yrs

posted by stefanti

4 comments posted 19yrs posted by stefanti

QuartusII: how to find out all the instances of a VHDL module in a design?

Hi All, currently I'm working with the Altera QuartusII 6.0sp1 and I can't find a way to find out ALL the instances of...

5 comments posted 19yrs

posted by Totti10

5 comments posted 19yrs posted by Totti10

sytemverilog supported by quartus 6.0?

the systemverilog is a power tools used in verification,i want to learn it.

0 comments posted 19yrs

posted by cppcpldfpga

0 comments posted 19yrs posted by cppcpldfpga