Migration from Spartan-2E to Spartan-3E

Hi,

I'm investigating the possibility to replace an Spartan-2E (xc2s400e) with an Spartan-3E (xc3s1200e) device on a PCB.

The core voltage drops from 1.8V to 1.2V. Has anyone experience regarding the footprint differences (easy/hard/impossible to adapt) and any other differences which must be taken into account?

Regards,

Stefan

Reply to
Stefan Tillich
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The footprint is different; beyond that, all parts can be routed.

As noted with the S3 vs S3E thread 2 days ago, there are a couple "gotchas" that you need to be aware of. There are only 4 IO banks, not

  1. While not necessarily a "problem" your existing design might dedicate eighths of the chip to a specific VCCIO rather than even quarters. Also, many of the S3E IOBs are input-only to save on die size; while this is fine for many, the loss of flexibility is felt.

I wouldn't expect the redesign to be a problem, otherwise.

I think S2 had tristate buffers but not S2E; either way, S3 and S3E don't have them. Memory blocks are now larger and DLLs are more functional as DCMs, both have "compatibility modes" for older designs. There's no longer a power-on surge. You also have new, cheaper programming ROM options.

I hope the conversion is fun.

Reply to
John_H

The blockrams in the S3 are bigger and S3 does not have tristate busses.

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Reply to
Nico Coesel

Read the FPGA configuration section CLOSELY. The JTAG pins and the dedicated configuration pins are powered from VCCAUX (2.5V). The other non-dedicated configuration pins are powered from Bank2 VCCO pins. I know of two designs this was over looked (1 was mine !!!) and it did cause problems that needed a board re-layout. My design was drawing MUCH more current than it should have and I tracked it down to this.

I wish Xilinx would put out a "Gottcha FAQ" that have the top changes from the previous family that will point out problems when moving to the new family.

Reply to
typhon62

Read the FPGA configuration section CLOSELY. The JTAG pins and the dedicated configuration pins are powered from VCCAUX (2.5V). The other non-dedicated configuration pins are powered from Bank2 VCCO pins. I know of two designs this was over looked (1 was mine !!!) and it did cause problems that needed a board re-layout. My design was drawing MUCH more current than it should have and I tracked it down to this.

I wish Xilinx would put out a "Gottcha FAQ" that have the top changes from the previous family that will point out problems when moving to the new family.

Reply to
typhon62

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