uBlaze prototype PCB UART issues

Hello all,

Forgive me in advance for the long plea for help.

Would anyone be kind enough to troubleshoot my implementation of the EDK 8.1i flow for my production board?

I have implemented a good deal of my project firmware on the Spartan 3 evaluation board with great success. However, upon receipt of my 3E based prototype hardware, I have had nothing but problems successfully porting my design from evalution hardware to prototype hardware.

NOTE: On occasion, the firmware will operate as expected on the prototype board ruling out (hopefully) any board level issues.

My issues seem to be more related to the EDK flow itself or perhaps my lack of understanding of aforementioned EDK flow.

## Physical Differences ## The only differences between the prototype hardware and the evaluation platform wrt the FPGA are as follows:

(1) 500E vs. 200 (2) 100MHz LVDS clock vs. 50 MHz

I have inserted the differential-to-single-ended buffers as per the Xilinx app note regarding differntial clocks.

## The Working Hack ## I can take the previous design targeted for the evaluation board (Spartan 3 Starter) and do the following:

(1) Change the target hardware to the Spartan 3E 500E (2) Insert the differential input buffer (3) Modify the evaluation board UCF to accomadate the prototype implementation

This method works. However, the boad rate (9600bps) is off by a factor of the clock speed multiple (x2).

## The Failed Flow ## Creating a new project targeted towards my prototype hardware (3E@100MHz) fails miserably. Despite repeated efforts across many variations on a theme, I can't even implement a STDIO RS232 interface executing the puked up diagnostic routines. PAR takes a rediculously long period of time and timing constraints seem to complicate the issue.

I'm sure I haven't provided enough pertinent information to characterize my problem. So, if anyone has any ideas or question which would lead me in the correct direction I'd be very appreciative. This exercise seems very straight forward and I'm at a loss as to why I'm having such a hard time doing something so simple.

Thanks :)

Reply to
mjackson
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put a single T flip flop to divide clock for baud rate.

Reply to
jacko

"mjackson" schrieb im Newsbeitrag news: snipped-for-privacy@k70g2000cwa.googlegroups.com...

Use DCM to get clock below 100MHz you should be able to run at some 75MHz or maye 83Mhz but hardly at 100MHz of course the UART baud settings have to match, but I think since 8.2 EDK is able to verify and warn if uart baud is wrong

also note that 8.2 may get better timing, but still hardly 100MHz sysclock for S3e

Antti

Reply to
Antti Lukats

Thank you for the responses. I will give this a shot.

Did I miss something in the data sheets/app notes though? I wasn't aware that the S3E had such limitiations on the upper bound for the sysclock on uBlaze processors.

Secondly, I have a licensed version of EDK 8.2, but was going to wait until my next project to upgrade my development platform (ISE, EDK, ChipScope, etc.). Do you advise upgrading EDK sooner rather than later?

Thanks

Reply to
mjackson

mjackson schrieb:

there is no direct upper bound freq limitations its rather complicate to give such numbers actually.

but as thumb guess if the system is not optimized for Xilinx marketing to give absolute total max sysclock then the system in S3e would have more chance to pass timing on sysclock below 100MHz

but, again it all depens what IP cores you have in and how you apply constraints and if you run xplorer script and multipass PAR, etc..

Its also hard to get 100Mhz on Virtex-4 (Xilinx advertizes 200MHz max MicroBlaze clock for ver 4) so timing trouble on realworld microblaze design in S3e at 100Mhz are just to be expected.

you should try EDK 8.2 and MB5 it has improved pipeline that should allow higher clocks, also it can run xplorer script on XPS system

Antti

Reply to
Antti

Thanks for the help Antti. Even by dividing the clock down from 100MHz to some 'reasonable' value of 50MHz to 75 MHz, I am still unable to get a functioning UART on this board when trying to implement a new design. The fact that it works when modifying designs intended for the evaluation board is literally driving me nuts. It seems rediculous that I will have to originate designs targeted for evaluation hardware and then hack my way to funcional designs on my own hardware.

I will try upgrading to 8.2 and see if that solves some issues. Consequently, is it possible that I'm exeeding the input range of the DCM at 100MHz? The more I fight with this, the less I think EDK is a time-saver when compared to a standard ISE flow.

Thanks again though.

Reply to
mjackson

mjackson schrieb:

after years of fight, I still fight (with EDK) - but I think EDK is actually getting better.

get 8.2 and let the xplorer script to optimize timing if you want to squeeze the max clock. getting the DCM to work in EDK isnt so simple, or maybe it is but it is equally simple to get something wrong and they want work.

I think as of some errata S3e early silicon had DCM input range maxed at 90MHz? production silicon is defently ok to use way higher inputs clocks

good luck and many succesful fights with EDK!

Antti

Reply to
Antti

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