Field-Programmable Gate Arrays

Generate 16MHz from 75MHz using DCM

Hi, We have an eval board with a spartan FPGA and a 75MHz XTAL Within ourt design, we require an accurate 16MHz clock....

4 comments posted 19yrs

posted by moogyd

4 comments posted 19yrs posted by moogyd

An implementation of a clean reset signal

Hello all, Following some discussion in these groups and reading a couple of articles (especially the first one turning...

47 comments posted 19yrs

posted by eliben

47 comments posted 19yrs posted by eliben

Just a matter of time

Over the years I have gotten a lot of junk email from Xilinx to email addresses that I have given out only to support a...

18 comments posted 19yrs

posted by gnuarm

18 comments posted 19yrs posted by gnuarm

Can I use MIG tool to generate memory controller for DIMM module of DDR SDRAM?

is MIG the tool to use or there are some other tools I am not aware of ? I want to use low profile 256M DIMM DDR-SDRAM...

0 comments posted 19yrs

posted by jetq5188

0 comments posted 19yrs posted by jetq5188

PLB/OPB Bus Access from ISE

Is there an easy way to access the PLB or OPB buses from XIlinx ISE without going through the PowerPC and EDK? I am usi...

1 comments posted 19yrs

posted by akcooper8

1 comments posted 19yrs posted by akcooper8

Xilinx ML310 logical analyzer

how to see the read signal in ML310? i know ChipScope can do it, but i think it's not easy to add it into my design. i...

0 comments posted 19yrs

posted by TaiYing

0 comments posted 19yrs posted by TaiYing

ISE timing errors

my basic design works perfectly. Now when I add a set of adders to the design I get timing errors in my design. I chang...

7 comments posted 19yrs

posted by dhruvakshad

7 comments posted 19yrs posted by dhruvakshad

logic analyzer signal tap 2 - writing data

hello i am a student, working on development kit nios 2 cyclone edition. i want to use the logic analyzer to import data...

6 comments posted 19yrs

posted by 1024.david

6 comments posted 19yrs posted by 1024.david

free CAN field bus IP for EDK ?

in order not to reinvente the wheel is there a free and publicly available CAN protocol IP for microblaze/EDK (8.1 eval...

7 comments posted 19yrs

posted by rponsard

7 comments posted 19yrs posted by rponsard

ADC card selection for C6713

Hi all I want to receive 70 MHz PM+BPSK modulated signal. Video bandwidth:138 kHz Modulation index for PM: 1.2 radian S...

0 comments posted 19yrs

posted by murselonder

0 comments posted 19yrs posted by murselonder

TTL signal to an FPGA I/O pin?

Hi, I'm sending a TTL pulse-width modulated signal to an FPGA I/O pin with the hope of sampling it at 10 MHz to create...

1 comments posted 19yrs

posted by xyz.interactive

1 comments posted 19yrs posted by xyz.interactive

Virtex-II Pro Platform FPGA : Assembling the modules

Hi, I am trying to do the partial reconfiguration. I almost came to the final step which is place and route of the logi...

20 comments posted 19yrs

posted by airthang

20 comments posted 19yrs posted by airthang

Input signal problem...

I have a differential data stream going into the FPGA via two pins. The two signals, data_p and data_n, connect to an I...

1 comments posted 19yrs

posted by mottoblatto

1 comments posted 19yrs posted by mottoblatto

Xilinx PowerPC & MicroBlaze Development Kit

Hi, Is there anyone who knows where can I buy XIlinx PowerPC & MicroBlaze Development Kit in european union ?? (DO-ML40...

6 comments posted 19yrs

posted by czeczek

6 comments posted 19yrs posted by czeczek

unexpected Xilinx TNM constraint behaviour

I'm seeing some unexpected behavior when using the Xilinx TNM constraint in a ucf file. I'm using the 8.2.03 version of...

2 comments posted 19yrs

posted by johnp3+nospam

2 comments posted 19yrs posted by johnp3+nospam