Field-Programmable Gate Arrays

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EDIF

Hi I am using synplify to synth a design with some xilinx core gen devices. get warnings on some of the core gen edif f...
2 comments posted 20yrs
posted by maxascent
2 comments posted 20yrs posted by maxascent

Generate 16MHz from 75MHz using DCM

Hi, We have an eval board with a spartan FPGA and a 75MHz XTAL Within ourt design, we require an accurate 16MHz clock....
4 comments posted 20yrs
posted by moogyd
4 comments posted 20yrs posted by moogyd

An implementation of a clean reset signal

Hello all, Following some discussion in these groups and reading a couple of articles (especially the first one turning...
47 comments posted 20yrs
posted by eliben
47 comments posted 20yrs posted by eliben

Just a matter of time

Over the years I have gotten a lot of junk email from Xilinx to email addresses that I have given out only to support a...
18 comments posted 20yrs
posted by gnuarm
18 comments posted 20yrs posted by gnuarm

PLB/OPB Bus Access from ISE

Is there an easy way to access the PLB or OPB buses from XIlinx ISE without going through the PowerPC and EDK? I am usi...
1 comments posted 20yrs
posted by akcooper8
1 comments posted 20yrs posted by akcooper8

Xilinx ML310 logical analyzer

how to see the read signal in ML310? i know ChipScope can do it, but i think it's not easy to add it into my design. i...
0 comments posted 20yrs
posted by TaiYing
0 comments posted 20yrs posted by TaiYing

ISE timing errors

my basic design works perfectly. Now when I add a set of adders to the design I get timing errors in my design. I chang...
7 comments posted 20yrs
posted by dhruvakshad
7 comments posted 20yrs posted by dhruvakshad

logic analyzer signal tap 2 - writing data

hello i am a student, working on development kit nios 2 cyclone edition. i want to use the logic analyzer to import data...
6 comments posted 20yrs
posted by 1024.david
6 comments posted 20yrs posted by 1024.david

free CAN field bus IP for EDK ?

in order not to reinvente the wheel is there a free and publicly available CAN protocol IP for microblaze/EDK (8.1 eval...
7 comments posted 20yrs
posted by rponsard
7 comments posted 20yrs posted by rponsard

ADC card selection for C6713

Hi all I want to receive 70 MHz PM+BPSK modulated signal. Video bandwidth:138 kHz Modulation index for PM: 1.2 radian S...
0 comments posted 20yrs
posted by murselonder
0 comments posted 20yrs posted by murselonder

TTL signal to an FPGA I/O pin?

Hi, I'm sending a TTL pulse-width modulated signal to an FPGA I/O pin with the hope of sampling it at 10 MHz to create...
1 comments posted 20yrs
posted by xyz.interactive
1 comments posted 20yrs posted by xyz.interactive

Input signal problem...

I have a differential data stream going into the FPGA via two pins. The two signals, data_p and data_n, connect to an I...
1 comments posted 20yrs
posted by mottoblatto
1 comments posted 20yrs posted by mottoblatto

Xilinx PowerPC & MicroBlaze Development Kit

Hi, Is there anyone who knows where can I buy XIlinx PowerPC & MicroBlaze Development Kit in european union ?? (DO-ML40...
6 comments posted 20yrs
posted by czeczek
6 comments posted 20yrs posted by czeczek