I have a differential data stream going into the FPGA via two pins. The two signals, data_p and data_n, connect to an IBUFDS internally. Now, is it possible to route that single-ended data output from the IBUFDS to 4 different ISERDES modules? I have tried, but map gives errors about having the source to the D input of an ISERDES driving other loads. Apparently you can't do this. But I need that data signal to go to 4 independently clocked ISERDES setups. I am trying to do data recovery via 4 phased clocks. Is there any way to do this without routing 4 differential pairs into the FPGA? Apparently the maximum number of IBUFDS's you can drive with the same input is 2.
thanks for any ideas.