Hi,
I'm sending a TTL pulse-width modulated signal to an FPGA I/O pin with the hope of sampling it at 10 MHz to create a binary signal that can be processed digitally. What logic function in VHDL do I have to use to sample this signal at the I/O pin at that required speed? Hopefully this is simple.
Thanks, A
Andrew
You need to pass this through a register or flip-flop to put the signal into you sampling frequency domain. You may get metastability oscillation effects on samples close to transition edges and a second flip-flop to sample the output of the first flip-flop is advisable before actual use in any designs.
Your sample will have a jitter on pulse width of +/- 1clock on the real width so make sure your sample rate is high enough such that this jitter does not cause you issues.
There are some links to useful web resources in our TechiTips part of our website here
John Adair Enterpo> Hi,
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