Field-Programmable Gate Arrays

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VHDL count error when cascading

I am using 3 * gal22v20's cant change them. Clocks are all wired together and ripple out is connected to the enable of...
2 comments posted 20yrs
posted by billybob_bonkashea
2 comments posted 20yrs posted by billybob_bonkashea

ISE 8.2 and partitions from command line

I'm trying to figure out if it is possible to use partitions using either command line flow (I want to integrate it int...
5 comments posted 20yrs
posted by ehliar
5 comments posted 20yrs posted by ehliar

Instantiating Altera M4K block without MegaWizard

Hello, I'm trying to write a VHDL video line buffer. I've done this several times before, but this time I have to write...
13 comments posted 20yrs
posted by robert.leune
13 comments posted 20yrs posted by robert.leune

Design of a programmable delay line

Hello, For a future project I need to design a programmable delay line. The specifications are: steps of +/- 1 ns, rang...
13 comments posted 20yrs
posted by Karel.Deprez
13 comments posted 20yrs posted by Karel.Deprez

Spartan 3 Starter Kit I/O ports

Hello, I am relatively new to VHDL design, and I bought this board as a first time learning kit. I was mainly intereste...
10 comments posted 20yrs
posted by nugentoffer
10 comments posted 20yrs posted by nugentoffer

.ise project files, episode N+1

> >Yet again I've had to completely re-build a project because >Navigator corrupted the .ise file and the backup versio...
0 comments posted 20yrs
posted by brimdavis
0 comments posted 20yrs posted by brimdavis

Open protocol USB JTAG cable

Hi everybody, I'm going to build a USB JTAG cable and I don't know what protocol should I use for communication. The on...
4 comments posted 20yrs
posted by goss
4 comments posted 20yrs posted by goss

a clueless bloke tells Xilinx to get a move on

The following is an informal letter to Xilinx requesting their continued efforts to increase the speed of their softwar...
29 comments posted 20yrs
posted by brannonking
29 comments posted 20yrs posted by brannonking

SMPTE310 interface

I am looking for ideas on how to implement SMPTE310 Tx and Rx interface. Algorithm/VHDL/Verilog examples would be helpfu...
2 comments posted 20yrs
posted by cbr_929rr
2 comments posted 20yrs posted by cbr_929rr

nicer code => slower code??

I was playing with this old design the other day and decided to "clean it up" a little bit (it was kinda messy). I move...
9 comments posted 20yrs
posted by burn.sir
9 comments posted 20yrs posted by burn.sir

BSD indi processor IP compiles at 283 LEs

hi 283 LEs 6% Cyclone II EP2C5T144C6 44 Warnings Still unverified. yes got it to compile at last after discovering a bi...
17 comments posted 20yrs
posted by jackokring
17 comments posted 20yrs posted by jackokring

Virtex-5 FX when ?

to my surprise I just heard comments about Xilinx giving up hard processor cores - well I think its not so, and that V5...
3 comments posted 20yrs
posted by Antti.Lukats
3 comments posted 20yrs posted by Antti.Lukats

This is great news

On the Xilinx Home Page XILINX OPENS DEVELOPMENT CENTRE IN INDIA TO STRENGTHEN GLOBAL R&D ECOSYSTEM
0 comments posted 20yrs
posted by emh203
0 comments posted 20yrs posted by emh203

Nios II interrupt

Hi, I am new to the Nios II core. I have built a simple system with a timer which is set as periodically timer. I have...
1 comments posted 20yrs
posted by someone
1 comments posted 20yrs posted by someone

How to accelerate bitstream file generation?

Hi, I am using Xilinx ISE software for an FPGA project. Every time I do a small change in the HDL code I have to regene...
3 comments posted 20yrs
posted by robertdb
3 comments posted 20yrs posted by robertdb