Hi,
I am using Xilinx ISE software for an FPGA project. Every time I do a small change in the HDL code I have to regenerate the bitstream file and the ISE software takes a long time to do the job. Is there a way to accelerate it? Is there a way to avoid synthesizing parts of the design that are untouched since the last synthesis? What about the rest of tue processes? Is it faster to use a batch file instead of using the software GUI?
Thanks, Robert
Yeah. It's called L1/2/3 cache. It costs several hundred dollars for a fair amount of it. If you can cut your compile times from 20min to
15min by purchasing a $1000 CPU, how long would it take the company to pay for that with the made-up time?You can resynth only part of the design currently. Using the GUI just select the subcomponent and compile that portion. The Map/Par tools support a similar functionality using what's called guide files. Last I heard Xilinx was working on a major upgrade of this feature. Search the news group for more info on it.
There is no difference (assuming parameters are the same).
I think I'll post a letter on this forum begging for more work on this...
Brann> Yeah. It's called L1/2/3 cache. It costs several hundred dollars for a
I would prefer to spend the money on a fast HDL simulator to check those small changes without having to generate a bitstream file.
-- Mike Treseler
Robert
Have a look at our TechiTip on incremntal synthesis here
John Adair Enterpo> Hi,
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