I am using Xilinx ISE software for an FPGA project. Every time I do a small change in the HDL code I have to regenerate the bitstream file and the ISE software takes a long time to do the job. Is there a way to accelerate it? Is there a way to avoid synthesizing parts of the design that are untouched since the last synthesis? What about the rest of tue processes? Is it faster to use a batch file instead of using the software GUI?