BSD indi processor IP compiles at 283 LEs

just retargeted to MAX II to see how it went. looks good.

386LEs 17% MAX II EPM2210F256C3

hi

MAX II EPM570T100C5 just fits at 68% utilizati> jacko wrote:

Changed design to only mirror P reg on super/user interrupt toggle pin, and got down to 303 LEs in the MAX II EPM570T100C5. This gives more free space for IO and control.

jacko schrieb:

MAX2 chips are WAY WAY WAY too expensive. just compare the Lattice XP3 pricing and features.

MAX2 has no onchip ram, thats the major problem.

Antti

Got it down to 222 LEs on the MAX II, not sure how to export to lattice devices from the altera tool, and how available is the lattice tool? Is it free???

jacko schrieb:

sure its free! (for selected devices)

if you wrote in VHDL or verilog then should be no problem just create a project with ispLEVER PN and add hdl sources!

Antti

i am quite new to the altera tool, and have not used the xilinix one or the lattice one, i am using schematic entry, and am not sure how to export a netlist. vhdl will not be used fro the forseable future. i use the lpm funcs quite a bit in the design, and expect to get 6 MIPS at

60MHz in max II. Does anyone know how to make the quartus II give out a netlist which can be input into another design tool? or is there a netlist to vhdl converter in the public domain?

what are the best size minimization options to place on quartus? to get good optimization?

i am not doing other peoples homework, as i am not rich by any means, i would consider doing vhdl piad, but who pays?

Hi

using FPGA vendor sch tools is ok in some cases, but it should not be used for developing IP cores - sch to hdl or edif conversion to not offer quality portable hdl from schematic entry.

so unfortunatly you may end up doing manual conversion or most likely it means you just have to rewrite it hdl from scratch.

if you think that your processor has some use at all then you should take that effort and do the conversion to VHDL (or verilog)

Antti

not a top priority for me at present, maybe some pay design later :)

cheers.

p.s. is there an altera specific IP section on there site as i can not find it if there?

I don't believe the free version includes any simulation capability. I asked my vendor very nicely and they provided a free, licenced version. I believe the license runs out periodically, but they have given me an update and I expect they will continue to do so. Unlike the Altera tools, it is not keyed to the NIC or other machine attribute, so it is very easy to get working.

Even though we have all the tools we need at work, I like to test new things at home and these free tools let me do that. It also lets me get around some of the work bureaucracy and gives me more freedom to try things.

Hi

Now at version indi16.3.0 fixed logical error and made improvements in cycle timing. slightly larger, but the older versions will not work due to the logical error pin held at ground. approx 370 logical elements. removed interupt facility cos this can be done with 2 indi cores and correct wait /busfree chaining.

have to work out how to promote clock, 40 pin external bus changes to test16 top level. compiling for larger chip 1270 series to be able to get IO devices on.

should work at 60MHz which is 12MIPS. the forth i'm developing will support device polling, and i have just written the arithmetic words.

cheers

or or

When you say 12 MIPS are you saying it takes 5 clock cycles to complete an instruction? That seems excessive. My CPU design is about 50% larger than yours, but it completes an instruction per clock cycle and can run at 77 to 100 MHz in current economy FPGAs. Why do you need so many clock cycles?

top level now 41 pin bus.

http-offline://indi.joox.net (no longer in use!!) Try

or

all instructions are load -> alu -> store (using the 1 memory bus) this would make a two cycle minimum. for 2 memory accesses. each memory access takes 2 cycles, this is due to 1 cycle data out or in settling time before 1 cycle latching time. this allows cheap external memory use, internal use could reduce mem io to 1 cycle, but not designed in yet. so total = 4 clock cycles so far. then 2 instructions come in one word so 2 cycles for fetch but only 1 equiv cycle per instruction. so grand total of 5 cycles per instruction.

is that clearer? the two cycle memory access also makes for an easier WAIT pin which halts the processor after the current memory access. memory access wait state insertion would have to occur via clock division.

I think it may work, got rid of many logic errors by simplyfying some logic and changing the external bus, moved to 5 cycle per instruction throughput in design while maintaining low complexity. This required the removal of RAS, CAS addressing easy direct support, but SRAM is best at 128KB maximum memory size ( except when using CS[1] to isolate stack memory from program and data memory. (( CS[0] selects program=0 or data=1 memory.but no dictionary extension can occur if CS[0] is used like this. ))

cheers.

p.s. when you must simply fit in 330 LEs then this is whats needed.

That is a big difference. My design only runs on internal FPGA memory. It is intended to be a chip controller, not a general purpose CPU.

What is the application for this design?

1. Open and Free Specification IP
2. For the hell of it
3. 2007 Christmas toy market, investigating options
4. 8-bit replacement of low complexity
5. 32 and 64 bit options should not be that hard to engineer. need to find best utility for extra 16 or 48 bits in instruction word.
6. test before manufacture in full custom as a 44-pin QFP.

there may be others. Any interested Fab $ 0.25 per chip royalty with right to use any utility ROM images and more complicated 32 and 64 bit technologies.

cheers

hi indi16.3.3 release:

less stringent timing requirements

60MHz 12 MIPS 332 LEs 30ns external memory for 60MHz 64MHz is target frequency for easy video generati> rickman wrote: