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VHDL count error when cascading

I am using 3 * gal22v20's cant change them. Clocks are all wired together and ripple out is connected to the enable of the next chip. After compiling the code the MSD decoder does not count correctly and appears to be taking 9/10 clk pluses to the enable causing it to run the fast on the 3rd chip. here is the original code there are no PCB error. Below that is a remodelled VHDL that is giving errors. Can anyone give me some insighty into this error. Thanks Rob

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity segment_cnt is

port(

clk,mr,en,pause, clk_in :in std_logic; segs :buffer std_logic_vector(6 downto 0); clk_out ut std_logic; rco : out std_logic );

end segment_cnt;

architecture behav of segment_cnt is begin

cnt_procrocess(clk, mr) begin if(mr='0') then segs

Reply to
rob
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The problem is rco is glitching. Since it is created from multiple signals, it can glitch depending on how these signals propagate through the logic. You should be able to see this with a logic analyzer. On hp analyzers, you needed to turn on glitch mode. But all three parts should be failing in the same way.

Making rco depend on clk is left as an exercise for the reader.

Not sure what you were trying to do with the remodeled VHDL, but it is the wrong approach.

Alan Nishioka

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Alan Nishioka

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Peter Alfke

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