Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Quartus II 6.0: System clock has been set back

I seem to have a licensing problem with the Quartus Web edition. I receive the error message: Warning: FLEXlm software...
14 comments posted 19yrs
posted by mike102de
14 comments posted 19yrs posted by mike102de

EDK / ISE versionning and interoperability

I purchased Spartan3E starter kit (for edu.) It is shipped with ISE8.1 and EDK8.1 Is 8.2 (with last patches) better tha...
1 comments posted 19yrs
posted by rponsard
1 comments posted 19yrs posted by rponsard

Quartus II 6.0

How can I do a "clean up project" with Quartus II 6.0? TIA, Frank
7 comments posted 19yrs
posted by frank.van.eijkelenburg
7 comments posted 19yrs posted by frank.van.eijkelenburg

Xilinx distributor in South East Asia

Hi all, I hope I'm posting in the right place. I'm newbie in FPGA and want to have a development board. My choice is Sp...
2 comments posted 19yrs
posted by kunilkuda
2 comments posted 19yrs posted by kunilkuda

75Mhz Spartan3e microblaze

hi i hvea a question about implementing a microblaze with ethernet. i'm using a spartan 3e 500 an edk8.2. i created a n...
10 comments posted 19yrs
posted by u_stadler
10 comments posted 19yrs posted by u_stadler

Xilinx-Modelsim on Linux

Hey there I have a lot of trouble finding directions/guides/manuals on how to get subject working. Anyone able to point...
13 comments posted 19yrs
posted by henrik.kirneh
13 comments posted 19yrs posted by henrik.kirneh

Antifuse, lower cost?

Does anyone have experience with antifuse fpgas? Are they lower cost than static ram fpgas? Thank you, Scott Moore
28 comments posted 19yrs
posted by nospam
28 comments posted 19yrs posted by nospam

New web page! www. indigitall.com

Dear all, Please visit my new web home page for RF design , and free schematics info. www. indigitall.com Best Regards,...
0 comments posted 19yrs
posted by rfdsolutions
0 comments posted 19yrs posted by rfdsolutions

Enterpoint PCI Core

Finally some details now on our website for those asking about the core. We have delayed the release to maximise the in...
0 comments posted 19yrs
posted by g1
0 comments posted 19yrs posted by g1

Spartan3A - internal flash configuration or not?

hi the features of S3A are so close to S3E that it makes one think - why? Why release a device that is so similar? I th...
4 comments posted 19yrs
posted by Antti.Lukats
4 comments posted 19yrs posted by Antti.Lukats

Two instances of Microblaze ...

Hi all, I have a microblaze processor that I've built using the EDK and afterwards simulated and it seems to work fine....
5 comments posted 19yrs
posted by me_2003
5 comments posted 19yrs posted by me_2003

Get Pedia

i am sorry if this is the wrong section . i just finished a huge website called www.this.explains.it and i need yo...
1 comments posted 19yrs
posted by cutemonication2
1 comments posted 19yrs posted by cutemonication2

Spartan 3 DCI

Hi, In Xilinx spartan 3, is it possible to drive both LVDS and SSTL on the same bank with DCI turned on for both IO Stan...
9 comments posted 19yrs
posted by yy7d6
9 comments posted 19yrs posted by yy7d6

VHDL count error when cascading

I am using 3 * gal22v20's cant change them. Clocks are all wired together and ripple out is connected to the enable of...
2 comments posted 19yrs
posted by billybob_bonkashea
2 comments posted 19yrs posted by billybob_bonkashea