FPGA comparision

You want a FPGA with 150.000 LUTs ? 75000 Slices ... and at low cost ? I must have mis-understood ...

But there is not that much manufacturer of FPGA ... If you currently have a model that fits your needs : - Lookup it's size in terms of LUTs/FF couple. - Check what "special resources" you're using like hard multipliers, DSP48, DCM, ... - Now check the Xilinx, Altera, Lattice, (Actel ?) websites for devices with about the same or superior LUTs/FF count and check if it has the other special resources you need. Think also that some of there resources could be implemented by logic ...

Also check out

Sylvain

Hi,

what quantities do you need? What kind of design is it?

Without knowing any details, I think you should try to get the LUT count down. I can imagine that a design that REALLY fills one of those large devices must have a quite long development time. So I suppose if you can already compile the design before you know which device you are targeting, I think there is a lot of potential there.

Thomas

"subint" schrieb im Newsbeitrag news: snipped-for-privacy@m7g2000cwm.googlegroups.com...

You are not going to get a device of this size as a low cost device unless you wait several years and several generations of low cost device. Even the very biggest low cost Spartan-3s and equivalents are not THAT low cost. The lowest cost option is several mid family parts to cover the size e.g. XC3S1500.

John Adair Enterpo> Hi,

Does your design need to be 150k tightly coupled LUTs running at 400 MHz?

Do you need massive memory? Any memory?

Consider partitioning your design into several smaller FPGAs, divided up per your parallelism or by functional blocks.

You can get 35k LUT FPGAs for a very reasonable price: Lattice ECP2-35, Xilinx XC3S1600E, Altera EP2C35. I choose these parts because I think they're more toward the "sweet spot" of the price curve. You can get larger devices in these families from Altera and Lattice or bump up the size in the Xilinx Spartan3 family (as opposed to the 3E just mentioned).

If you need large amounts of on-chip memory or multi gigabit communications, the new Lattice ECP2M series warrants serious consideration.

These devices are all designed for cost over speed. depending on the complexity of your system, 66 MHz to 200 MHz system designs are achievable, not 400 MHz type speeds. Typically, higher design speed is achieved through careful coding representative of well-seasoned FPGA designers. ASIC designers often don't have the speed pressure that FPGA folks have but you can find strong expertise in both camps.

So - how much are you willing to work in order to save money? Can you achieve what you want by improving your design approach (particularly if you have a very low system speed) or by creative partitioning into multiple FPGAs?

Good luck in your endeavors.

- John_H

That's because all FPGA/CPLD suppliers use a different 'unit of measure' when classifying their devices. There is currently no good unit of measure that can be used to compare across different manufacturers...but read on.

OK.

There are alternatives. If you have a design and it has been synthesized to target Xilinx then 'all you need to do' is take that same design and synthesize it to an Altera device family, Lattice device family, Actel, etc. When you do this you'll get a report from each synthesis effort that tells you how many logic resources of are used. The units of measure will be in whatever units the supplier calls them thus avoiding the generic (and sometimes misleading) conversion from brand X units to brand A, brand L, brand whatever.

Once you have the tools from the various suppliers (or have something like Synplify which can target them all) the process is straight forward. The catch is in the phrase 'all you need to do....'. If you have taken advantage of any Xilinx specific primitives in your design you'll have to come up with a vendor neutral approach to eliminate the Xilinx specific parts so that you can even run the synthesis to target the other devices.

If you find that you have a 'lot' of Xilinx specific primitives and the effort to make the design vendor neutral is too high just to make a determination of which device to target than what you can do is come up with a vendor neutral design that in some fashion mimics roughly what you want to accomplish but maybe doesn't have all of the logic implemented. Then run through the various tools to see how many logic resources get used. Even though what you've synthesized is not your entire design it should be enough for you to develop the conversion factors so that you can compare resource usage among the various suppliers.

Once you've completed this effort you should be able to say precisely which Actel, Altera, Lattice, Xilinx, etc. part your design will fit into and compare prices directly.

The other thing to keep in mind when you strip out vendor specific stuff though are just what things you're stripping out and if they are 'special' to that part. Things like multipliers and PLLs come immediately to mind here. You'll have to mentally keep track of these 'special' things if the other supplier parts don't have them...and what impact that will mean to your design if you need them. For example, multipliers can be synthesized with logic cells (but are usually going to be slower than a hard multiplier) but PLLs can not be synthesized at all so you're design flat out won't work if you need them.

KJ

fyi, the largest LatticeECP2M device has 95K LUTs, 5.3Mb Block RAM, and

hope this helps. Regards, Bart Borosky, Lattice