Hi, I need a help in static timing analysis for DDR interface to network processor . Processor say that its timing is as per JEDEC standard.
For Read i will be use tSD (avg.) =3D (tDQSQ + tDV) =F7 2 and able to find the setup margin and the hold margin.
But in the Write i am not able to calculate the same. Controller and DDR SDRAM say that it will provide/need 0.45 ns setup and hold time. I donot have any margin in that case. Can you let me know how do the do timing analysis for the write cycle. =20 Thanks and regards Pinku