Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Taking forever to synthesise (XILINX ISE 8.1i)

I am implementing an extremely old logic design (circa 1965!) on a Xilinx Virtex 4 (XC4VLX25). For those interested - i...
15 comments posted 20yrs
posted by davidroberts
15 comments posted 20yrs posted by davidroberts

Virtex-II Pro CRC Test Data

I've written a program to calculate the CRC of Virtex-II Pro bit stream and I'm having trouble validating my results. T...
1 comments posted 20yrs
posted by dpmontminy
1 comments posted 20yrs posted by dpmontminy

clock multiplexor device

Hi, I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke the Virtex-II series they now offer the...
2 comments posted 20yrs
posted by maerchenprinz
2 comments posted 20yrs posted by maerchenprinz

Dual Port RAM

Hi I am trying to infer a Xilinx dual port block ram with differen address and data widths. I want to infer it in my co...
66 comments posted 20yrs
posted by maxascent
66 comments posted 20yrs posted by maxascent

Stratix to PC communication

Hi, I am an undergrad student attempting to build a software defined radio device on a Stratix EP1S80 DSP Development B...
2 comments posted 20yrs
posted by bartzenbeggar
2 comments posted 20yrs posted by bartzenbeggar

image processing

hi to all, I'm developing a filter for imaging with matlab. In few days the code will be completed but I don't understo...
2 comments posted 20yrs
posted by lerbacattivanonmuoremai
2 comments posted 20yrs posted by lerbacattivanonmuoremai

Safe Routing

Hallo, I should develop a safety-critical application using Xilinx fpga. The system should be immune from matrix interc...
1 comments posted 20yrs
posted by ccghh
1 comments posted 20yrs posted by ccghh

Spartan3E clk/BUFGMUX warning

Hey, I'm using a XC3S500E-FG320 and let the PAR choose the clk pins itself with the right IOSTANARDS, then i locked the...
0 comments posted 20yrs
posted by yttrium
0 comments posted 20yrs posted by yttrium

SystemVerilog interface: virtual and ref

Hi all, When studying SystemVerilog, some book said 'virtual' is used to get the reference of the interface. But why th...
3 comments posted 20yrs
posted by zhushenli
3 comments posted 20yrs posted by zhushenli

Hardware mapping of algorithms

Hello, all -- I'm beginning to do some work in the efficient mapping of intensive algorithms (high orders of complexity...
2 comments posted 20yrs
posted by entanglebit
2 comments posted 20yrs posted by entanglebit

Virtex-4 & Wifi

Hi All, What is the easiest/best approach to attach Wifi to Virtex-4 (using from Linux)? Id' like to use some longer ra...
1 comments posted 20yrs
posted by zcsizmadia
1 comments posted 20yrs posted by zcsizmadia

Stratix II basic questions

Hi,there is any Stratix II user here? I'm involved in a hardware design for an EP2S90 device. I didn't ever used such a...
4 comments posted 20yrs
posted by piclist9
4 comments posted 20yrs posted by piclist9

Question about generic usage?

Hi, I am learning VHDL from Mike's example Uart.vhd in ISE 8.2. For behavioral simulation, I can run Modelsim smoothly....
1 comments posted 20yrs
posted by rxjwg98
1 comments posted 20yrs posted by rxjwg98

Usage of RAMB16 prmitives

Hi, I am trying to make a multi core processor design on board of virtex 4 family. I have 2 processors so i believe tha...
0 comments posted 20yrs
posted by vbhanu
0 comments posted 20yrs posted by vbhanu