I've written a program to calculate the CRC of Virtex-II Pro bit stream and I'm having trouble validating my results. Testing it against an existing bit stream, I do not get the right CRC result but I'm not sure if it's my calculations or how I am choosing which data is incorporate into the CRC. I've based my code on the Virtex Series Configuration Architecture Users Guide (XAPP151) and the Virtex-II Pro and Virtex-II Pro X FPGA Users Guide (UG012).
There are a few other posts in the forum regarding Xilinx CRC calculations. They suggest that I check bit order, reset the CRC at the proper times, and include the register address as part of the word that is feed into the CRC calculation. I've double checked and believe that I'm doing all of these correctly.
Does anyone know of some test data that I can use to test my CRC calculation? If I could test 1 or 2 calculations and validate that my CRC calculation are correct, I could eliminate the calculation as the cause of the problem. I know that there are a couple of CRC-16 calculators online, but I do not get the same results as they produce. I'm not sure if they are not designed to handle a 36 bit input, or if my calculations are wrong.
Any help or suggestions would be greatly appreciated.
Thanks,
David