Hallo, I should develop a safety-critical application using Xilinx fpga. The system should be immune from matrix interconnect switch changes (soft-errors) during operation, otherwise, if a switch changes the interconnection, it should go into a safe state.
There is a way to implement fail safe interconnections (pip), in example setting some parameters using PAR?
I already read the manual, but I don't have found such information. There lots of parameters about timing, but it's not clear about safe implementation.
I read also about scrubbing and readback, but I was wondering if PAR could be able to do it.
It is possble to know how PAR works at low level, or it's secred and covered by patents?
Many Thanks Marco T.