Field-Programmable Gate Arrays

SPDIF receiver

Hi Im planning to design an SPDIF receiver for implementation on Spartan 3 FPGA , But im not sure how to go about the de...

9 comments posted 19yrs

posted by aramosfet

9 comments posted 19yrs posted by aramosfet

Nios 2 application running from external ram

Hi, I have a bootloader running from internal ram (m4k blocks). I also build a standalone application to run from exter...

3 comments posted 19yrs

posted by someone

3 comments posted 19yrs posted by someone

DSP48 carry logic for multi-precision addition

Hi there, I am working on a high-speed (500 MHz, Virtex 4, speedgrade -12) and multi-precision adder (unsigned) capable...

2 comments posted 19yrs

posted by gueneysu

2 comments posted 19yrs posted by gueneysu

How to configuration 2 FPGAs mit one cable?

hallo, i have 2 FPGAs(both Xilinx Virtex-4) on one Board, and only one Cable(Platform Cable USB). How can i configuratio...

5 comments posted 19yrs

posted by uvbaz

5 comments posted 19yrs posted by uvbaz

FPGA's for Ethernet?

Hi all I'm a design engineer trying to evaluate the large number of possibilities for adding Ethernet to our embedded s...

8 comments posted 19yrs

posted by tschoepflin

8 comments posted 19yrs posted by tschoepflin

FFT help

Hi. I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 points (can be generic too)). Can Anybody help m...

7 comments posted 19yrs

posted by Jaksa1984

7 comments posted 19yrs posted by Jaksa1984

How stable is the internal clock of a Xilinx CPLD?

Hi, Where can I find a specification on how stable the internal clock of Xilinx's CPLDs (in this case the XC9572-7) is?...

5 comments posted 19yrs

posted by c.j.w

5 comments posted 19yrs posted by c.j.w

xup virtex2 pro

Hello, > I am using xup virtex2 pro with xc2vp30 fpga and I am trying to send data > between two boards. > I do not wan...

1 comments posted 19yrs

posted by nmichou

1 comments posted 19yrs posted by nmichou

Profibus implementation?

Is there any implementation of the profibus protocol for FPGA/CPLD known? DP V0 for cyclic traffic is sufficient. Prefe...

0 comments posted 19yrs

posted by janvi

0 comments posted 19yrs posted by janvi

Question about importing modules to XPS.

Hi, all: I want to incorporate moduleA and moduleB to XPS and connected them with microblaze. ModuleA and ModuleB have...

1 comments posted 19yrs

posted by hy34

1 comments posted 19yrs posted by hy34

Programming Virtex II Pro Eval Board

Hi, I hope someone would be able to help me with my issue. I have a Xilinx Virtex II Pro Eval board from Avnet. The boa...

3 comments posted 19yrs

posted by ramakrishnan.vijayakumar

3 comments posted 19yrs posted by ramakrishnan.vijayakumar

xilkernel cache

hi i have a micorblaze projet on a spartan 3 wit 8 k instruction an data cache linked with the ddr ram. the memory test...

0 comments posted 19yrs

posted by u_stadler

0 comments posted 19yrs posted by u_stadler

PC configuration for best Xilinx ISE performance

Hello, I want to buy a new PC and I will use it mainly for Xilinx ISE. What is the best configuration? Does Xilinx ISE s...

2 comments posted 19yrs

posted by maybetooparanoid

2 comments posted 19yrs posted by maybetooparanoid

Picoblaze simulation

Does anyone know how to simulate the picoblaze processor in modelsimXE(xilinx specific version) Is it possible?

1 comments posted 19yrs

posted by aramosfet

1 comments posted 19yrs posted by aramosfet

Taking forever to synthesise (XILINX ISE 8.1i)

I am implementing an extremely old logic design (circa 1965!) on a Xilinx Virtex 4 (XC4VLX25). For those interested - i...

15 comments posted 19yrs

posted by davidroberts

15 comments posted 19yrs posted by davidroberts