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How stable is the internal clock of a Xilinx CPLD?

Hi,

Where can I find a specification on how stable the internal clock of Xilinx's CPLDs (in this case the XC9572-7) is? For example tolerance, and drift of the frequency for ambient temperature. I can't find it in the product specs, and also not on Xilinx's website (to my surprise). The only thing the data sheet says is that f_SYSTEM has a min-value of

83.3. I also can't find anything about how to connect this system clock to a signal in my VHDL code.

I will use the CPLD to generate a PWM signal for control of a servo, and therefore the exact length of the pulses, in absolute time, is critical. If the internal clock is not considered reliable enough I would have to use an external chyrstal oscillator circuit. I could probably at least tolerate an error of a couple of percent of the frequency.

Thanks in advance, Carl

Reply to
c.j.w
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Reply to
Peter Alfke

I think I can see a miss-match here :) The f_system is the maximum value the Chip is guaranteed to clock (external Clock) at (usually with some given test pattern, to make it a usefull number )

It is NOT a spec value for some internal clock oscillator!!.

So, yes, you will have to provide an external Osc, with Sq wave drive.

-jg

Reply to
Jim Granville

Reply to
Peter Alfke

OK, thanks - actually I was considering whether there really was an internal clock - I asked a lab assistant, who told me there was. I figured it had to be the f_SYSTEM - but it's not :-).

I'll use an external oscillator circuit. Thanks everyone for helping me out.

Regards Carl

Reply to
c.j.w

I have actually built one out of a chain of inverters before and I would say a few things...

1) It was cool, but the frequency was all over the place. 2) As the manufacturing process changed so did my circuit's operation. It made it real hard to support over the 5 years the product was shipping. I think we saved $0.80 per board, but spent $200K over 5 years recertifying the products due to die changes.

Trevor

Reply to
Trevor Coolidge

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