SPDIF receiver

Hi Im planning to design an SPDIF receiver for implementation on Spartan 3 FPGA , But im not sure how to go about the design,Does any one have ideas ? Thank u

Reply to
aravind
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I did a quick Google search and found some very informative entries at Wikipedia. To get the low level format description I had to click through to the AES/EBU description and even more detail is available at one of the references given.

This should not be a difficult design to figure out, but there are details that require attention depending on your application.

Reply to
rickman

One big detail is are you just receiving the data, or are you also recovering a clock to feed to downstream codecs?

Reply to
Jeff Cunningham

I want to receive the data from spdif and convert it to I2S format to shift out the audio data to a dac such as cs4334.How do i sample the spdif signal ,synchronize it and convert the biphase mark code to normal 16 bit audio data in a register. I've done all the basic stuff in vhdl like multiplexed 7 segment display drivers,simple programs on picoblaze processor,etc.

Reply to
aravind

How *not* to do it:

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(That's my design so I can say that :)

HTH,

--
Ian

"Tamahome!!!" - "Miaka!!!"
Reply to
Ian

The data stream is BMC which is very easy to decode. You just need to consult some references and it should be very obvious. You need to sync your data recovery to the transitions between the bit cells. Get the value of the input following the rising or falling edge. Wait 3/4 bit time and sample the input again. If they match, you have a zero bit, if they are different you have a 1 bit. Then wait for the next edge on the input. You will be bit cell synchronized after sampling a zero bit.

The SPDIF data stream is simply the data with some framing around it. If you read a few references the structure is also very simple and easy to parse. A simple counter with a synchronization circuit should suffice.

It may not be obvious, but you need to use the data stream clock to generate the clock for your DAC. If you don't, you will either drop data or have to live with a lot of jitter in the sample clock which causes much audio distortion.

The digital aspects of this design are very straightforward, the analog aspects are not.

Reply to
rickman

does your design support only 44.1khz ?if yes what modifications have to be done to support 48khz

Reply to
aravind

The downstream DAC will need something like a 128 or 256 FS clock. You will need some sort of state machine to recognize when a flag character is being received. Then you can enable some combinatorial logic such that the trailing edge of the flag generates a FS reference edge for an external PLL such as a 74HC4046. Then use the PLL to multiply the frequency to generate the (typically) 256FS DAC clock reference.

You can then use the 256FS signal to clock your SPDIF receiver logic. Because the clock is locked to the data stream, you already implicitly know where the beginning middle and end of the bit cells are, so demodulating the FM data is just recognizing if there was a transition in the middle of the bit cell. You can then shift the data into a shift register, etc., all under control of the state machine.

Alternatively, if you have a local clock several times greater than the SPDIF bit rate, you can make a fancier state machine that recognizes edges, counts states to figure out where the bit cell boundaries would be and so on. This all digital approach removes the need for an external analog PLL, but can't provide a low jitter clock reference for your DAC.

You might also consider using an external SPDIF receiver from Cirrus or AKM or others, though that may take the fun out of it.

Reply to
Jeff Cunningham

Yes, it's hard-wired (is that the right term for a CPLD?) to 44.1KHz timing. To do other rates would require changes to the biphase decoder thresholds at least, the rest should just follow the signal timing.

--
Ian

"Tamahome!!!" - "Miaka!!!"
Reply to
Ian
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Reply to
ilia_2s

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