Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

C3188A - 1/3"Digital Output Colour Camera Module

Hello, Is there anyone who interface the C3188A - 1/3" Digital Output Colour Camera Module with an fpga. I am waiting fo...
3 comments posted 19yrs
posted by hikmetkoca
3 comments posted 19yrs posted by hikmetkoca

Code for Verilog 8bit * 8bit pipelined multiplier

I am looking for an 8bit * 8 bit pipelined multiplier. The algorithm I am trying to implement involves: 1 of the 8bits...
1 comments posted 19yrs
posted by stephen.horsford
1 comments posted 19yrs posted by stephen.horsford

shaping aynchronous signal

I have to build a block acting like a monostable with programmable duration: ____________ | | ________ In: _|___ -->| |...
0 comments posted 19yrs
posted by bergnoli
0 comments posted 19yrs posted by bergnoli

add-compare-select

Hi! I'm trying to implement an add-compare-select (ACS) unit in a Spartan3 but I am not satisfied with the speed. The c...
6 comments posted 19yrs
posted by REMOVEallesCAPITALS
6 comments posted 19yrs posted by REMOVEallesCAPITALS

XUP-V2Pro banking rule problem

I'm working on a XUP-V2Pro project which needs both the VDEC-1 video capture card and a 256-MB memory module. The Base...
7 comments posted 19yrs
posted by tbfleming
7 comments posted 19yrs posted by tbfleming

bidirectional bus

Hi, is there anyone who have a clue on how a synthesizer will do the RTL for bidirectional bus inside your logic? As fa...
6 comments posted 19yrs
posted by alessandro.basili
6 comments posted 19yrs posted by alessandro.basili

tri0 GSR = glbl.GSR;

Hello, I am using Cadence NC-Sim to simulate my design. The compilation is OK. After the elaborator process I got the m...
2 comments posted 19yrs
posted by julien.lochen
2 comments posted 19yrs posted by julien.lochen

Microblaze + uClinux issues

Hi all, I've been struggling for two days now to get xapp730 from Xilinx to work. I've built the hw (wo FSL as it seems...
3 comments posted 19yrs
posted by e8johan
3 comments posted 19yrs posted by e8johan

ZBT Bus

Hi I have an 18-bit bus to a ZBT memory but when I P&R it in Xilinx it set half the bus to TRISTATE and the other to BI...
1 comments posted 19yrs
posted by maxascent
1 comments posted 19yrs posted by maxascent

ISE bugs or newbie error?

Hi. When I try to see the RTL Schematic, Xilinx ISE hangs and it is not possible to stop it. Furthermore I get the foll...
1 comments posted 19yrs
posted by jpistor
1 comments posted 19yrs posted by jpistor

drive LVDS clocks with a spartan3

Hello, I work as Design Engineer at Bull SAS in France (Server Design and Development). I saw a webcase on the web in w...
1 comments posted 19yrs
posted by julien.lochen
1 comments posted 19yrs posted by julien.lochen

abel to vhdl converter

I have a JED file for an old PAL device and I have to put this design in a FPGA. Is there a tool that can read the JED f...
8 comments posted 19yrs
posted by lingamaneni.naveen
8 comments posted 19yrs posted by lingamaneni.naveen