Is there a mindelay constraint keyword or something similar? My fpga is producing 1 byte with a clock signal going to the pads and I need the data to be on the pads for 5ns, then clock. So I just need a way to delay the clock until data is definitely ready.
by the way I'm using virtex 4 and I'm having sampling issues. The signal it produces is not that clean for some reason.
produces is not that clean for some reason.
If the data is there for a whole cycle the easy way is to latch it on the opposite clock edge. That should be near the middle of the clock cycle. If that doesn't work, try the other suggestions.
-- glen
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