I apologize if this questions has been answered already. I was unable to find an answer in my search through this group.
If you have any experience using LVDS with Xilinx FPGAs, please help.
Q: If I have a LVDS input, must my top-level entity specify both the N and P ports, or is there a way to specify that a port should use LVDS in a constraint file and have the Xilinx tools infer the correct buffers?
I know something to this effect works:
... input_p : std_logic; input_n : std_logic; ... port map ( I => input_p, IB => input_n, O => internal_single_ended_signal);
But, is there a way to just have the following (plus specify that input is LVDS in a constraints file) and have the xilinx tools infer what is in the code above?:
... input : std_logic; ...
Thank you in advance for your help.