query in gate level simulationin quartus s/w 6.0

I have two problems in verilog gate level simulation

1) I want to preserve hierarchy between entity.Where will be this setting in quartus s/w 2) The gate level netlist has time scale has 1ps/1ps.test bench and host models have 1ns/10ps.I want to change the time scale of netlist.is it feasible for changing the delays after # symbol.How to do it kumar
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1) Use the Assignments->Settings->EDA Tools Settings dialog. Enter your simulation tool name and then click the More Settings button. Then change the valueof Maintain Hierarchy to On.

2) Use the Assignments->Settings->EDA Tools Settings dialog. Set Format for output etlist to Verilog. Then change the time scale settings right next to it.

Then regenerate the netlist.

Hope this helps, Subroto Datta Altera Corp.

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Subroto Datta

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