Latest threads in Field-Programmable Gate Arrays

How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?

Hi all, in other words, is there an easy way to avoid FPGA attempt to configure? thanks florent

3 19yrs

florent.peyrard

3 19yrs florent.peyrard

approximation of an exponential ramp?

In an interview from 97, Bob Yannes the designer of MOS 6581 (aka "SID") said the following aboud the chips ASDR envelo...

5 19yrs

burn.sir

5 19yrs burn.sir

linking two fpga boards

I have a ready built design with a cyclone device offering nothing more than some (around 5 maybe) unconnected io pins...

4 19yrs

fpgaengineerfrankfurt

4 19yrs fpgaengineerfrankfurt

Writing output signals to text file (VHDL)?

Hello, I am using FFT v3.2 core from Xilinx. I have Xilinx ISE/Model Sim. The outputs of the core are xk_re and xn_re....

9 19yrs

m.vitaliy

9 19yrs m.vitaliy

Some questions about FFT implementation

Hello, I am working with FFT v.3.2 from Xilinx. Some questions relate directly to that core, some do not. 1. Why is blo...

9 19yrs

m.vitaliy

9 19yrs m.vitaliy

impossible opb_emc hack?

I got my self stuck in that I have a V4 design with a 16-bit flash and a 32-bit peripheral device on the same external...

4 19yrs

someone

4 19yrs someone

Current programming hardware does not support Active Serial programming mode

I get this error trying to program a serial device using a homemade ByteBlaster II cable as described in Altera's "Byte...

0 19yrs

nevo_n

0 19yrs nevo_n

JTAG programming of Altera Cyclone and CONF_DONE

All, I'm having an extraoridnarily difficult time with my first FPGA project and am very frustrated. I have a board des...

10 19yrs

nevo_n

10 19yrs nevo_n

Using Jtag for general Communications

Hi, I would like to send some data back via my jtag cable from my spartan-3 board to the computer. I have read the arti...

0 19yrs

googlinggoogler

0 19yrs googlinggoogler

How to develop custom opb devices for Microblaze?

Folks, I have an EDK(*1) based project that utilizes the Microblaze, along with several peripherals connected via OPB (...

5 19yrs

beagle197

5 19yrs beagle197

computer vision projects for open cores

I was thinking of implementing some computer vision or neuro-morphic VHDL designs and then posting them on open cores,...

0 19yrs

wallge

0 19yrs wallge

50 MSPS ADC with Spartan 3 FPGA - clock issues

Hello, I'm in the middle of a project which involves digitizing and decoding baseband NTSC composite video. Right off t...

12 19yrs

sp_mclaugh

12 19yrs sp_mclaugh

Barrel shifter in Virtex4?

Hi. I'm trying to implement a fast 128-bit barrel shifter in a Virtex4 device. The obvious way is a 7-level cascade, ea...

1 19yrs

jetmarc

1 19yrs jetmarc

FFT on Virtex-II Pro (how to download .dat file?)

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as...

2 19yrs

m.vitaliy

2 19yrs m.vitaliy

Xilinx platform flash data sheet confusion (ds123) for clocking

page 21 schematic shows "CLK" driving the FPGAs, but note 5 say "CLKOUT" is used to drive the FPGA's CLK input, any clue...

2 19yrs

fpga_toys

2 19yrs fpga_toys

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