Field-Programmable Gate Arrays

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approximation of an exponential ramp?

In an interview from 97, Bob Yannes the designer of MOS 6581 (aka "SID") said the following aboud the chips ASDR envelo...
5 comments posted 19yrs
posted by burn.sir
5 comments posted 19yrs posted by burn.sir

linking two fpga boards

I have a ready built design with a cyclone device offering nothing more than some (around 5 maybe) unconnected io pins...
4 comments posted 19yrs
posted by fpgaengineerfrankfurt
4 comments posted 19yrs posted by fpgaengineerfrankfurt

Writing output signals to text file (VHDL)?

Hello, I am using FFT v3.2 core from Xilinx. I have Xilinx ISE/Model Sim. The outputs of the core are xk_re and xn_re....
9 comments posted 19yrs
posted by m.vitaliy
9 comments posted 19yrs posted by m.vitaliy

Some questions about FFT implementation

Hello, I am working with FFT v.3.2 from Xilinx. Some questions relate directly to that core, some do not. 1. Why is blo...
9 comments posted 19yrs
posted by m.vitaliy
9 comments posted 19yrs posted by m.vitaliy

impossible opb_emc hack?

I got my self stuck in that I have a V4 design with a 16-bit flash and a 32-bit peripheral device on the same external...
4 comments posted 19yrs
posted by someone
4 comments posted 19yrs posted by someone

JTAG programming of Altera Cyclone and CONF_DONE

All, I'm having an extraoridnarily difficult time with my first FPGA project and am very frustrated. I have a board des...
10 comments posted 19yrs
posted by nevo_n
10 comments posted 19yrs posted by nevo_n

Using Jtag for general Communications

Hi, I would like to send some data back via my jtag cable from my spartan-3 board to the computer. I have read the arti...
0 comments posted 19yrs
posted by googlinggoogler
0 comments posted 19yrs posted by googlinggoogler

How to develop custom opb devices for Microblaze?

Folks, I have an EDK(*1) based project that utilizes the Microblaze, along with several peripherals connected via OPB (...
5 comments posted 19yrs
posted by beagle197
5 comments posted 19yrs posted by beagle197

computer vision projects for open cores

I was thinking of implementing some computer vision or neuro-morphic VHDL designs and then posting them on open cores,...
0 comments posted 19yrs
posted by wallge
0 comments posted 19yrs posted by wallge

50 MSPS ADC with Spartan 3 FPGA - clock issues

Hello, I'm in the middle of a project which involves digitizing and decoding baseband NTSC composite video. Right off t...
12 comments posted 19yrs
posted by sp_mclaugh
12 comments posted 19yrs posted by sp_mclaugh

Barrel shifter in Virtex4?

Hi. I'm trying to implement a fast 128-bit barrel shifter in a Virtex4 device. The obvious way is a 7-level cascade, ea...
1 comments posted 19yrs
posted by jetmarc
1 comments posted 19yrs posted by jetmarc

FFT on Virtex-II Pro (how to download .dat file?)

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as...
2 comments posted 19yrs
posted by m.vitaliy
2 comments posted 19yrs posted by m.vitaliy

FFT on Virtex II Pro (how to download .dat file?)

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as...
0 comments posted 19yrs
posted by m.vitaliy
0 comments posted 19yrs posted by m.vitaliy