Xilinx platform flash data sheet confusion (ds123) for clocking

Note 5 says there are two ways to drive CCLK. The schematic shows an external oscillator (using dotted lines) to show one way. The other method is not shown in the schematic. The CLK pin of the XCFxxS is an input. CLKOUT is only available on the larger parts (8 Mbits up).

Which is what I presumed when I did the layout, and it means that the schematic is wrong, IE should have CLKOUT for PROM 0, since the schematic implies that is an output, and the note should say that it's wired to CLK for the optional configuration with an external clock.

Gabor wrote: