Field-Programmable Gate Arrays

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booting from isocm

Hi, Does anyone have a design example to share of Power PC booting from ISOCM? :) Any information is welcome as well......
0 comments posted 19yrs
posted by eascheiber
0 comments posted 19yrs posted by eascheiber

Virtex4 : cleaner signals?

Anyone have tips on having the Virtex 4 generate cleaner signals? I have 8 data lines coming out from the header IOs. T...
11 comments posted 19yrs
posted by seabass950
11 comments posted 19yrs posted by seabass950

config prom power

Hi all I have a remote module which I can only easily get 2.5V to. Powering a xilinx or altera FPGA from this is easy b...
0 comments posted 19yrs
posted by colin_toogood
0 comments posted 19yrs posted by colin_toogood

Tarfessock1

First picture of Tarfessock1, minus cardbus covers, now on our website for those that are interested in our little cardb...
10 comments posted 19yrs
posted by removethisthenleavejea
10 comments posted 19yrs posted by removethisthenleavejea

Partial reconfiguration

Hi all, does anybody know how partial reconfiguration is carried out in new Xilinx FPGAs (Spartan3 and Virtex4)? These...
3 comments posted 19yrs
posted by isd_mod
3 comments posted 19yrs posted by isd_mod

DDR2 DIMM memory termination resistors?

Hi, everyone I am designing a FPGA PCB board with one DDR2 dimm memory slot. As current project will only need single d...
3 comments posted 19yrs
posted by ssc3k
3 comments posted 19yrs posted by ssc3k

Give me job :)

Hello. I've implemented few crypto algorithms in FPGA and I found this exciting - it require very different way to thin...
1 comments posted 19yrs
posted by tenteric
1 comments posted 19yrs posted by tenteric

System ACE PROG_B and INIT pins

can someone tell me what these pins do? I'm trying to build a module with system ace on board, and trying to program th...
0 comments posted 19yrs
posted by sutejok
0 comments posted 19yrs posted by sutejok

@(posedge clk)

Hi, What does a statement like @(posedge clk) synthesise to? if i write:- input b; output c; a=b; @(posedge clk); c=a;
5 comments posted 19yrs
posted by vittal.patil
5 comments posted 19yrs posted by vittal.patil

Aurora v2.5

I've just used the Core Generator to customise an Aurora 16 bit streaming interface for a V2P. The resulting code has t...
1 comments posted 19yrs
posted by enquiries
1 comments posted 19yrs posted by enquiries