Latest threads in Field-Programmable Gate Arrays

Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC

Hi, yesterday I solved a problem while integrating the embedded TEMAC of an V4FX60 with an RGMII PHY after some try and...

2 19yrs

cpmetz

2 19yrs cpmetz

booting from isocm

Hi, Does anyone have a design example to share of Power PC booting from ISOCM? :) Any information is welcome as well......

0 19yrs

eascheiber

0 19yrs eascheiber

Virtex4 : cleaner signals?

Anyone have tips on having the Virtex 4 generate cleaner signals? I have 8 data lines coming out from the header IOs. T...

11 19yrs

seabass950

11 19yrs seabass950

config prom power

Hi all I have a remote module which I can only easily get 2.5V to. Powering a xilinx or altera FPGA from this is easy b...

0 19yrs

colin_toogood

0 19yrs colin_toogood

Tarfessock1

First picture of Tarfessock1, minus cardbus covers, now on our website for those that are interested in our little cardb...

10 19yrs

removethisthenleavejea

10 19yrs removethisthenleavejea

Partial reconfiguration

Hi all, does anybody know how partial reconfiguration is carried out in new Xilinx FPGAs (Spartan3 and Virtex4)? These...

3 19yrs

isd_mod

3 19yrs isd_mod

DDR2 DIMM memory termination resistors?

Hi, everyone I am designing a FPGA PCB board with one DDR2 dimm memory slot. As current project will only need single d...

3 19yrs

ssc3k

3 19yrs ssc3k

Give me job :)

Hello. I've implemented few crypto algorithms in FPGA and I found this exciting - it require very different way to thin...

1 19yrs

tenteric

1 19yrs tenteric

spartan3E : which differential inputs level fits CAN2B bus level ?

Hi groups, for a CAN2B core demo : which differential input model for xilinx (spartan3E) can fit at best a 80C250 tranc...

3 19yrs

rponsard

3 19yrs rponsard

ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)

Hi all. I have created a simple application to test ISRs. This application is very similar to the application example p...

3 19yrs

alfmyk

3 19yrs alfmyk

Integrate VHDL Cores in Microblaze (Spartan 3E Starter Kit)

Hi, I am trying to integrate a ps2 core (for Keyboard) to Microblaze with the Create/Import Wizard. I cannot get this i...

0 19yrs

pbantunez

0 19yrs pbantunez

How to read data from intel strata flash using microblaze?

Hello all, This is the first time i am working with Flash. Has anyone experienced with reading data from intel strata f...

4 19yrs

guybye

4 19yrs guybye

System ACE PROG_B and INIT pins

can someone tell me what these pins do? I'm trying to build a module with system ace on board, and trying to program th...

0 19yrs

sutejok

0 19yrs sutejok

@(posedge clk)

Hi, What does a statement like @(posedge clk) synthesise to? if i write:- input b; output c; a=b; @(posedge clk); c=a;

5 19yrs

vittal.patil

5 19yrs vittal.patil

Aurora v2.5

I've just used the Core Generator to customise an Aurora 16 bit streaming interface for a V2P. The resulting code has t...

1 19yrs

enquiries

1 19yrs enquiries

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