Hi all, does anybody know how partial reconfiguration is carried out in new Xilinx FPGAs (Spartan3 and Virtex4)? These devices have no internal three-state buffers or bus macros, so is there a way to avoid contentions during reconfiguration?!?
Thanks, Antonio
Antonio,
Actually, the Spartan3 and Virtex4 do have bus macros available for use with ISE 8.x. The only place I know of on the web that has the latest bus macros is Xilinx's Partial Reconfiguration Early Access Software Tools website. There are early access tools, so you need to apply and be granted access. I believe Xilinx requires a certain level of local support to be in place before granting access. You can apply for access at
I hope this helps,
David
A.D. wrote:
Thanks a lot David! Antonio
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