Hi, What does a statement like @(posedge clk) synthesise to? if i write:-
input b; output c; a=b; @(posedge clk); c=a;
Hi, What does a statement like @(posedge clk) synthesise to? if i write:-
input b; output c; a=b; @(posedge clk); c=a;
Verilog introductions are TERRIBLE about clarifying what's synthesizable and what's not. Verilog is two languages in one -- one procedural language that is useful for controlling simulations, and one hardware description language which can be synthesized. Your sequence of instructions might be useful for an input stimulus file, but not for describing hardware.
-- Ben Jackson AD7GD http://www.ben.com/
Assuming your 'a' is a reg it will systhesize to one DFF with input b and ouput c.
It is a bad idea. Synthesis tools will reject this code, and although a simulator will process it, nobody reading your code will be able to understand or maintain it.
To help you understand it, I'll explain what it does in simulation...
1) It waits for an event on a, b or clk 2) It sets a=b 3) It waits for a rising clock edge 4) It sets c=a 5) It loops from step 1.
I thought this was an intriguing question because I did not know how @(*) deals with clk in the case above so I looked it up in the Verilog standard. (IEEE Std 1364-2005 to be exact, section
9.7.5.)It turns out that @(*) should add all (net and variable) identifiers to the sensitivity list unless at least one of the following is true:
The following is an example from the standard: always @* begin // equivalent to a(b) @(i) kid = b; // i is not added to @* end
So the example above should be modified as follows:
1) It waits for an event on a or bI could also note that the version of Modelsim I'm using (6.2b) does seem to add identifiers in event expressions to the sensitivity list unfortunately.
/Andreas
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