I've just used the Core Generator to customise an Aurora 16 bit streaming interface for a V2P. The resulting code has the core placed on the bottom edge of the device when I put it on the top edge during customisation. Has anyone else noticed this?
TIA.
Rog.
I haven't seen this particular issue, but Xilinx has just confirmed to me that Aurora v2.5 can generate wrong code if an existing core is recustomizied. I found this when playing with a simplex core for V4FX.
/Mikhail
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