I thought that some people on this newsgroup might be interested in two small hacks I've written recently:
--------------------------------------------------------------------------- xdlanalyze.pl:
Shows statistics about an XDL file (or NCD file) as in the following example: (I'm not aware of any Xilinx command that will print this kind of (hierarchical) information about a place and routed design, please enlighten me if I've missed something.)
$ perl xdlanalyze.pl dafk.xdl XDLAnalyze V1.1 by Andreas Ehliar Analyzing the file dafk.xdl...................................................
+-------------+--------+--------+--------+-----------+--------+--------+ | Module | LUTS | FF | RAMB16 | MULT18x18 | IOB | DCM |
+-------------+--------+--------+--------+-----------+--------+--------+ | / | 64 | | | | 216 | | | cpu | 5065 | 1345 | 12 | 4 | | | | dma0 | 654 | 254 | 1 | | | | | dvga | 816 | 755 | 4 | | | | | eth3 | 2995 | 2337 | 4 | | | | | jpg0 | 1682 | 681 | 2 | 13 | | | | leela | 684 | 552 | 4 | 2 | | | | pia | 9 | | | | | | | pkmc_mc | 219 | 122 | | | | | | rom0 | 111 | 3 | 12 | | | | | sys_sig_gen | | 6 | | | | 2 | | uart2 | 824 | 346 | | | | | | wb_conbus | 618 | 10 | | | | |
+-------------+--------+--------+--------+-----------+--------+--------+ | Total | 13741 | 6411 | 39 | 19 | 216 | 2 |
+-------------+--------+--------+--------+-----------+--------+--------+
This allows you to see the resources used by different modules in your design without having to resynthesize just that part of the design. This also means that we can get resource usage of individual modules after the module has been optimized for a certain design. Some fuzziness will remain because logic from more than one module might have been placed in the same LUT, there is nothing I can do about this. You can also show the hierarchy in more detail as in the following example:
$ perl xdlanalyze.pl dafk.xdl 1 XDLAnalyze V1.1 by Andreas Ehliar Analyzing the file dafk.xdl...................................................
+-----------------------------+--------+--------+--------+-----------+--------+--------+ | Module | LUTS | FF | RAMB16 | MULT18x18 | IOB | DCM |
+-----------------------------+--------+--------+--------+-----------+--------+--------+ | / | 64 | | | | 216 | | | cpu | 1 | | | | | | | cpu/dwb_biu | 10 | 72 | | | | | | cpu/iwb_biu | 64 | 73 | | | | | | cpu/or1200_cpu | 4441 | 987 | 2 | 4 | | | | cpu/or1200_dc_top | 208 | 40 | 5 | | | | | cpu/or1200_ic_top | 182 | 38 | 5 | | | | | cpu/or1200_immu_top | 11 | 33 | | | | | | cpu/or1200_pic | 32 | 38 | | | | | | cpu/or1200_tt | 116 | 64 | | | | | | dma0 | 617 | 235 | | | | | ... many lines removed ... | uart2/wb_interface | 65 | 80 | | | | | | wb_conbus | 618 | | | | | | | wb_conbus/arb | | 10 | | | | |
+-----------------------------+--------+--------+--------+-----------+--------+--------+ | Total | 13741 | 6411 | 39 | 19 | 216 | 2 |
+-----------------------------+--------+--------+--------+-----------+--------+--------+
If run against a .NCD file it will use xdl -ncd2xdl to automatically convert a design to .XDL before analyzing it.
You can download it at
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colorized_signals.tcl:
A modelsim hack which allows you to add all signals in a certain module to the wave window and change the color of inputs, outputs and inouts so that they are different than internal signals. Screenshots are available at
You can download it at
Tested with Modelsim 6.2b in Linux.
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I hope someone will find this useful :)
/Andreas