Field-Programmable Gate Arrays

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solder mask for fpga dissipation

Hi guys, I have to produce a PCB with a couple of FPGA on it and I was wondering if the solder mask right under the FPG...
10 comments posted 19yrs
posted by alessandro.basili
10 comments posted 19yrs posted by alessandro.basili

ppc elf data and vectors sections

Hi, I did an objdump on my elf file and I got an text section of approx 4KB, vectors section approx 8KB and data sectio...
1 comments posted 19yrs
posted by eascheiber
1 comments posted 19yrs posted by eascheiber

ERROR:MDT - ERROR FROM TCL:- linux_mvl31 ()

Hi, I start to work on FPGA Embedded system. I am trying to port the MonstaVista Linux on the system. First I built the...
0 comments posted 19yrs
posted by airthang
0 comments posted 19yrs posted by airthang

EDK, header file modified and problem

Hi I am writing some C codes for Microblazes on EDK. Problem is that If I do not change the header file, it works fine....
0 comments posted 19yrs
posted by pasacco
0 comments posted 19yrs posted by pasacco

Frequency divider?

I need to divide my clock by 10, can someone confirm if my verilog module will work: //divide oscillator clock by 10 (x...
15 comments posted 19yrs
posted by <222>
15 comments posted 19yrs posted by <222>

DSP or FPGA for high-speed image processing?

Hi, I am going to start a project of onboard high-speed CMOS image processing. I am goint to perform certain *block mat...
4 comments posted 19yrs
posted by ggkyori
4 comments posted 19yrs posted by ggkyori

PowerPC_EDK to ISE

I am trying to import a PowerPC design from EDK 7.1 to ISE 7.1 Project Navigator. While the design is working just fine...
3 comments posted 19yrs
posted by
3 comments posted 19yrs posted by

Netlist Simulation for PPC (Virtex-4 FPGA)

Has any one done netlist simulation . Virtex-4 FPGA . Power PC Based Architecture. Boot , Instruction and Data code res...
0 comments posted 19yrs
posted by dudyalas
0 comments posted 19yrs posted by dudyalas

Xilinx PMCD+DCM reset question...

In looking at the Virtex-4 documentation for the PMCD, Xilinx shows a simple connection from the DCM to the PMCD. They...
3 comments posted 19yrs
posted by johnp3+nospam
3 comments posted 19yrs posted by johnp3+nospam

uClinux bootloader on Spartan-3e Starter Kit

Hi all, I was abble to compile working uClinux core for the Spartan-3e Starter Kit. I was abble to program on board Fla...
2 comments posted 19yrs
posted by jerzy.zielinski
2 comments posted 19yrs posted by jerzy.zielinski

Xilins ISE Re-Creating Projects

Hi A couple of months ago I had to move up to ISE 8.2 once 7.1 stopped meeting my timings. Since I moved I have had not...
9 comments posted 19yrs
posted by marc_ely
9 comments posted 19yrs posted by marc_ely

Xilinx ISE 8.2.3 - Re-Creating Projects

Hi A couple of months ago I had to move up to ISE 8.2 once 7.1 stopped meeting my timings. Since I moved I have had not...
4 comments posted 19yrs
posted by marc_ely
4 comments posted 19yrs posted by marc_ely

Lcd Block Diagram - Vhdl - On Fpga.. help!

hi, i'm working on fpga .. wanna make an vhdl code for lcd .. but as a block diagram .. using mux ( multiplexer ) and co...
0 comments posted 19yrs
posted by riverofmusic
0 comments posted 19yrs posted by riverofmusic