Re: unexplainable Problem on Spartan 3

You might try a different approach. You say you have verified all the pieces separately. If so, you know the code segments are written correctly. This means the problem is in how you have them connected or how you combined them. So try it in small steps. Simplify to your LED flasher alone. Make sure that works on the chip. Then combine the LED flasher with one other module that you can test. Make sure the LED flasher works and then verify the other module. Next add another module and test. You can do this serially or you can do a binary search by splitting the group of modules in half and testing the two halves separately. If one works and the other does not, you can procede to split the non-working group in two. But if your problem has to do with how you are combining the modules it is likely that none of the groups will work.

I seriously doubt that you will get anyone to test your code for you. It will go much faster if you learn debugging techniques yourself. You might be surprised at how simple it can be to find problems. A lot of times the hard part is realizing that it is realy very simple even if it is a lot of work.

snipped-for-privacy@gmail.com wrote:

Greetings to all ! > > I started programming with VHDL two months ago. Now I want to implement > a project on a Spartan 3 (XC3S50 VQ100). The software I=B4m using is the > ISE Webpack 8.2.03i (Application Version: I.34).
Reply to
rickman
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Thomas -

You have no timing constraints in your .ucf file. At a minimum, you should put in period constraints for your clocks.

RR

snipped-for-privacy@gmail.com wrote:

Reply to
Randy Robinson

First of all thanks for your replies ! I read a lot about debugging strategies and I did it similar as suggested. By now I corrected the error but I couldn=B4t define the exact position of the bug. I think it has something to do with the .ucf-file. I will now add the clocking period. So I can be sure that the interaction between the part is acting as suspected.

Now I want to use 2 DCMs to produce three phase-shifted and period-delayed clocks(receiving-part) and three clocks that aren=B4t. For the delay I used a counting-structure combined with BUFGCEs. I also though about usind a shift register but I think it would cause more skew. Has anyone a better idea?

Here=B4s the code:

DELAY_CLK_PS: process(CLKX8) begin if CLKX8'event and CLKX8 =3D '1' then if DELAY_PS_EN =3D '1' then if CNT =3D MAX_CNT then U2_CLKX1_PS_ENABLE

Reply to
thomas.neitzel

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