Latest threads in Field-Programmable Gate Arrays

Surface mount ic's

Does anyone know what is needed to work with surface mount ic's, what sort of starting price tag are we talking about? (...

39 19yrs

39 19yrs <smount>

PPC PLB <=> FPGA fabric

Hi all, I want to load my PPC program in an external SRAM connected to the PLB bus on the PPC. But I fail to find any s...

4 19yrs

dontreplytothisaddy

4 19yrs dontreplytothisaddy

help on Xilinx USB download cable

hi, Can anyone tell me how to repair the xilinx download cable? I have ever bought two USB cables from xilinx, they hav...

2 19yrs

iamsunlei

2 19yrs iamsunlei

Help with ISE (multi-source in unit error)

Hi, I'm pretty new to verilog and I am trying to write code to compute a mean and store it in RAM. I update the ram eac...

5 19yrs

ian.peikon

5 19yrs ian.peikon

xilinx xc9536?

Hello, there are some pins on xilinx xc9536 which are called global clock1/2/3 global reset, etc, where are these explai...

12 19yrs

<highZ>

12 19yrs <highZ>

hi......

can any one tell em dcm or clock tree and if multiple cloks r there in my design how to handle it bufg concept in clock...

1 19yrs

karanashu

1 19yrs karanashu

Memory controller design

Hi, I would like to connect many independent data source/targets to a common data stream. There will be a 36-bit static...

7 19yrs

wyderski

7 19yrs wyderski

How to deal with the negative value

I want to transmit a set of data R to FPGA board. The ABS|R|

3 19yrs

threeinchnail

3 19yrs threeinchnail

ERROR:NgdBuild:604

Hi People , I am using a custom BRAM , but it is not getting synthesised , it keeps giving the error that ERROR:NgdBuil...

3 19yrs

get2venu

3 19yrs get2venu

(Improve Verilog skill) Recommend CPU core with good document and coding?

Hi all, These days, I found my Verilog code reading speed is not fast like my C/C++ reading speed. It take me a lot of...

3 19yrs

zhushenli

3 19yrs zhushenli

Tools available to split the design into multiple FPGAs.

Hi, i would like to know is there is any tools available from xilinx or other to split the design into multiple fpga and...

2 19yrs

subin.82

2 19yrs subin.82

SUNDANCE FPGA CONFIGURATION

Hi, has anybody worked with a fgpa/dsp board solution from "sundance"? I need some information about the configuration...

3 19yrs

pbantunez

3 19yrs pbantunez

For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2

Hello, After completing the PART 1 of this tutorial you can now connect and verify the FX2 functioning as well as estab...

0 19yrs

mansoor.naseer

0 19yrs mansoor.naseer

SPI slave problem

Hello Folks, I'm writting a slave SPI code for my FPGA and very sure that my master is generating the right SPI but som...

13 19yrs

mankin18

13 19yrs mankin18

system ace - ERROR: IMPACT:477 - what is this?

impact:477 the bsdl for device 'UNKNOWN' is out of date does anyone have any idea? I have this error when working with...

1 19yrs

sutejok

1 19yrs sutejok

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays