For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2


After completing the PART 1 of this tutorial you can now connect and verify the FX2 functioning as well as establish the End Point FIFO transfers in Bulk mode. However, all the transactions have taken place within the scope of FX2. Majority of the time, it is required to connect the FX2 with an external peripheral for instance FPGA or any micro processor to transmit and receive data in a custom product. We will now look at how to setup FX2 in synchronous slave FIFO mode with an FPGA.

In this setup, we will first ensure that the clock common to both FX2 and FPGA should be provided by the FX2 itself. So the first experiment should be to setup FX2 for internal clock source running at 12/24/48MHz as you wish. You will have to set just two registers CPUCS (CPU control and status) and IFCONFIG (interface configuration) registers for this experiment. Write a small program as given below to establish clkout (you will be required to add EzUSB.lib from the C:\Cypress\USB\Target\Lib\LP\EZUSB.LIB folder, I am using FX2LP so the folder LP, select appropriate folder for your devices):

************************************************************************************************ #include "C:\Cypress\USB\Target\Inc\fx2.h" #include "C:\Cypress\USB\Target\Inc\fx2regs.h"

void main (void) { CPUCS = 0x12; IFCONFIG |= 0x40;

while (1) ; }

************************************************************************************************* Now if you create the hex file using Keil uVision and burn it to the FX2 using control panel => download, and check CLKOUT pin (pin5 in 56 pin package, pin100 in 100 pin package, pin1 in 128 pin package), you should be able to see a valid clock signal running at 24MHz. CPUCS will set the clock to 48 MHz and enable CLKOUT with 0x12. Try changing it to 0x0A for 24MHz.

The IFCONFIG does nothing but to set the internal clock frequency for the GPIF/FIFO at 48MHz. The rest of the bits remain default.

You can also take this signal into FPGA and output it onto any general purpose header pin and check whether the FPGA is reading through the clock out signal correctly using an oscilloscope. While programming, you need to ensure that FX2 is programmed first, then FPGA is programmed. Also, if the clockout signal is resetting to 12MHz after FPGA programming, then you should set the reset pin connecting the fPGA and FX2 to high (FPGA will otherwise go low after programming and will cause the FX2 to reset which is active low).

Now you have established a time base which will be used for designing FPGA master read and write state machines which will read/write from slave FIFO in FX2.

Till next time,

Hope it helps.

Mansoor Naseer

Reply to
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.