Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

(-1)*xn operation in FPGA

Hi, in C programming,it's easy to get a negative value of any variables, as minus -xn; in FPGA, suppose it's 16bit 2's...
3 comments posted 19yrs
posted by iamsunlei
3 comments posted 19yrs posted by iamsunlei

Use Multi-cycle Path or Pipeline?

Hi all, In normal design we'd like to pipeline large comb logic to pipelined design. But I heard there is Multi-cycle P...
5 comments posted 19yrs
posted by zhushenli
5 comments posted 19yrs posted by zhushenli

Build an FPGA programmer cable

Hi! Until now I have only worked with FPGA development boards (Altera, Xilinx). I do this only for educational purposes...
6 comments posted 19yrs
posted by timos
6 comments posted 19yrs posted by timos

First Picture of Craignell Modules

For those asking first photo of DIL FPGA modules Craignell1/2/3 are now on our website. Modules have a very tiny packag...
9 comments posted 19yrs
posted by g1
9 comments posted 19yrs posted by g1

Basic questions about digital phase locked loop

Hey, everyone, Hope you are doing great! I just started learning about digital phase locked loop. I have a lot of thing...
3 comments posted 19yrs
posted by tryyourbestok
3 comments posted 19yrs posted by tryyourbestok

email protection in the list

Since I started posting to this list under my current adress, I am receivin tons of spam mails every day. I thought, th...
3 comments posted 19yrs
posted by fpgaengineerfrankfurt
3 comments posted 19yrs posted by fpgaengineerfrankfurt

Problem with unused pin on Spartan 2E

I have a mature design on a spartan2300E. It has some unused pin - by that I mean there are no references to thoses pin...
8 comments posted 19yrs
posted by blinkingCursor
8 comments posted 19yrs posted by blinkingCursor

query

iam using mentor graphics modelsim6.2d for running verilog codes,can anyone tell me how to use code coverage in batch
1 comments posted 19yrs
posted by premsundari
1 comments posted 19yrs posted by premsundari

data transfer from fast APB clock domain.

Hello. I have a peripheral with an AMBA APB interface. The issue that I am facing is that of clock domain crossing. The...
3 comments posted 19yrs
posted by marcoa.castellon
3 comments posted 19yrs posted by marcoa.castellon

Xilinx 2-D DCT core (Where?).

I'm running 8.2.03i, and expected to find the 2-D DCT core when I fired up the core generator. It either wasn't there, o...
0 comments posted 19yrs
posted by pfraser
0 comments posted 19yrs posted by pfraser

Problems with 7:1 LVDS Tx using OSEDES (Xilinx)

Hi, I am trying to make 7:1 LVDS Tx for a display solution (XGA and SXGA) and trying to use the approach as specified i...
3 comments posted 19yrs
posted by raonpc
3 comments posted 19yrs posted by raonpc