data transfer from fast APB clock domain.

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Hello.

I have a peripheral with an AMBA APB interface.
The issue that I am facing is that of clock domain crossing.
The processing logic in the peripheral is required to operate at a
relatively slow clock frequency, but the clock frequency of the APB
interface can be 4 to 5 times that of the slow clock domain.
I have been considering the two clock domains as asynchronous with
respect to each other, even though the faster clock is generated from
the slow clock by means of a PLL; therefore, the phase relationship
between the two clock should be constant.

My problems lies in the fact that APB has no signal to hold the bus in
the case where the data from a write cycle to the slow clock domain has
not yet been registered by the slow clock when a second write cycle
starts to happen.

I am considering to options:
1) Have the Configuration Registers clocked with the fast clock signal
and only have event signals generated by a write or a read cross the
clock domain boundary.

2) Buffer data with a FIFO and synchronize the control signals to the
slow clock domain.

Any suggestions would be appreciated.
Thank you in advance.
Best Regards,
Marco.


Re: data transfer from fast APB clock domain.

Quoted text here. Click to load it

AMBA APB version 3 has such a signal I believe, pready.

Cheers,
Jon


Re: data transfer from fast APB clock domain.
Yes, thank you for pointing out the availability of PREADY in APB
version 3.0
I had read about that in a different message thread.
Unfortunately, as one may expect I am limited by the fact that I am
interfacing to an AMBA 2.0 system.

Marco.

Jon Beniston wrote:
Quoted text here. Click to load it


Re: data transfer from fast APB clock domain.
Use your APB clock as the clock for your slower circuit, it will use
slightly more power but your static timing problems will handled by the
tools.

Next, use a "data ready" status bit in your slave so that the master
knows when its should expect to be able to read valid data.  APB wasn't
meant to hold for slaves, the ARM has to deal with this by using some
kind of data ready signal.  If the software guy gives your a hard time
offer to write the I/O routine for him.

marco wrote:
Quoted text here. Click to load it


Site Timeline