I have a peripheral with an AMBA APB interface. The issue that I am facing is that of clock domain crossing. The processing logic in the peripheral is required to operate at a relatively slow clock frequency, but the clock frequency of the APB interface can be 4 to 5 times that of the slow clock domain. I have been considering the two clock domains as asynchronous with respect to each other, even though the faster clock is generated from the slow clock by means of a PLL; therefore, the phase relationship between the two clock should be constant.
My problems lies in the fact that APB has no signal to hold the bus in the case where the data from a write cycle to the slow clock domain has not yet been registered by the slow clock when a second write cycle starts to happen.
I am considering to options:1) Have the Configuration Registers clocked with the fast clock signal and only have event signals generated by a write or a read cross the clock domain boundary.
2) Buffer data with a FIFO and synchronize the control signals to the slow clock domain.
Any suggestions would be appreciated. Thank you in advance. Best Regards, Marco.