I have been asked, many times, how an ASIC "gate" compares to a FPGA "gate."
Now don't just groan, and hit ignore, bear with me (if you have an opinion or feel like a comment).
An ASIC "gate" (in my feeble mind) is 4 transistors, arranged as a NOR, or a NAND. From that basic element, you can make everything else, or at least represent the complexity of everything else.
Now take a FPGA. Look at the LUT. Take the 4 LUT in Virtex 4. It is16 memory cells. Is that 32 "gates"? What happens when you use it as a 16 bit LUTRAM, or SRL16? Isn't that closer to 64 "gates"?
If I use the LUT as a 2 input NAND gate, then it is one "gate" and I have to use some LUTs as small gates, so I obviously can't count all my LUTs as 64 gates!
Take the DCM. How many "gates" would it take to do that?
The DSP48. How many "gates"?
So, I have always decided to stay away from any serious engineering evaluation of "gates" vs "gates" as being a no-win discussion. But is it? Is there no real comparison that can be made?
Obviously, people use FPGAs. And, they use ASICs. Sometimes they do one, and then replace it (oh my!) with another. Is a 2 million "gate" ASIC equal to a XC4VLX25? or a XC4VLX200? Or, not even the largest FPGA we can make (XC5VLX330)?
I have seen customers "fit" their 2 million "gate" ASIC into a LX25, so from just that one customer's point of view, 2 million "gates" could be realized by 24,000 4-LUTS, 24,000 DFF's, 1.3 Mb of BRAM, 8 DCMs, and 48 DSP48 blocks. That is about 6 million bits of configuration bits.
Is the answer a "range" from 2 million gates (depending on who is doing the conversion) can sometimes go into FPGAs that range in size of 5:1?10:1?