Hi all,

I need to implement DC blocker in FPGA. Data samples are coming at every clock cycle.

My original idea was to implement high pass filter as in formula below:

y[n] = x[n] - x[n-1] + p*y[n-1]

However it seems to me that I cannot achieve this with the given data rate. I am unable to calculate output by the time when I need it in feedback loop for the next sample.

Is there some way to do this that I don't see? If not, I was thinking of finding mean value of signal and subtracting it from signal in order to clear DC.

However, I do not know how to determine appropriate number of samples for this and do i do this by FIR filtering with all coefficients equal to

1/N?Thank you in advance.

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