I am receiving this error in xilinx ERROR:Xst:899 - "../../rtl/dff.v" line 7: The logic for does not match a known FF or Latch template.
The code being synthesizd is:
module dff(output reg qout, input clok, rst,d,enf); always @(posedge clok or negedge rst) begin if(enf) begin if(rst) qout
What are you trying to do with signal "enf"? The way you coded it, enf overrides the asynchronous reset as well as the clock. Also since you coded reset as a negedge signal, it should be tested for being low rather than high. If "enf" is supposed to be a clock enable it should be part of the else clause like:
always @ (posedge clok or negedge rst) begin if (!rst) // active low async reset qout
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.