Field-Programmable Gate Arrays

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9.1i in Red Hat Enterprise Linux AS 64-bit

I was trying to installing Xilinx ISE 9.1i full version on RHEL 4 AS 64-bit and I got following errors: error while loa...
2 comments posted 19yrs
posted by xingzhiwen
2 comments posted 19yrs posted by xingzhiwen

or1k on spartan 3, 400K gate version

hi, i tried to implement or1K processor on spartan 400K chip, but it sysnthesizes to 4834 slices, but the chip has only...
6 comments posted 19yrs
posted by manusha
6 comments posted 19yrs posted by manusha

xilinx x2pro ppc custom crt0

Hi I am trying to compile a file with custom initialization routines. Mainly to write my own assembler interrupt routin...
1 comments posted 19yrs
posted by st
1 comments posted 19yrs posted by st

problem with microblaze gcc toolchain

Hi I'm starting to use the gnu mb-gcc compiler but I get this error message: mb-gcc test1.c /cygdrive/d/xilinx/gnu/micr...
0 comments posted 19yrs
posted by manuel-lozano
0 comments posted 19yrs posted by manuel-lozano

DFT Details....

Hi Friends, I would like to know more details on DFT,DFM.DFx and DFT tools used.. Please helpme to share some course ma...
0 comments posted 19yrs
posted by paratal.srinivas
0 comments posted 19yrs posted by paratal.srinivas

SystemC hangs abruptly

ello guys. I am trying to learn systemC in school. If anyone is not familiar with it please check out the link. Its an...
1 comments posted 19yrs
posted by aijazbaig1
1 comments posted 19yrs posted by aijazbaig1

BFM and Verilog custom IP

I'm attempting to use the CoreConnect BFM with a Verilog-based PLB peripheral (for a PowerPC-based design). I used the...
0 comments posted 19yrs
posted by kunals.spam.account
0 comments posted 19yrs posted by kunals.spam.account

query in P&R of FPGA

I am a doing design.I am emulating FPGA.My problem is whenever i change one line of code(verilog) on top model i am get...
4 comments posted 19yrs
posted by vsrpkumar
4 comments posted 19yrs posted by vsrpkumar

Reconfiguration

Hi all, I was trying to reconfigure two circuits, I see that because of the interconnects/routing, the bitstream differe...
1 comments posted 19yrs
posted by bharadwaj.sr
1 comments posted 19yrs posted by bharadwaj.sr

data OCM BRAM Issues

There have been some previous threads concerning problems with the OCM bus, like these two:...
2 comments posted 19yrs
posted by njoroge
2 comments posted 19yrs posted by njoroge

Xilinx Interconnects/Routing

Hey All... Is there a way to decode the interconnect/Routing algorithm used by Xilinx???? I see that the XDL file gives...
11 comments posted 19yrs
posted by bharadwaj.sr
11 comments posted 19yrs posted by bharadwaj.sr

circle generation algorithm

Hi, Does anyone know how to implemtent circle generation algorithm in verilog? i want to implement it in spartan 3 kit,...
8 comments posted 19yrs
posted by ecbharat
8 comments posted 19yrs posted by ecbharat

ISE 9.1 SAY YOURS OPINION

Hi, I'm just wondering how many people here are using ISE 9.1. Could you post your experience here? Antii what do you t...
15 comments posted 19yrs
posted by francesco_poderico
15 comments posted 19yrs posted by francesco_poderico

XST broken for XC9536?

I was a TA for an introductory VHDL lab yesterday and I encountered a very weird problem. In the source code included b...
7 comments posted 19yrs
posted by ehliar
7 comments posted 19yrs posted by ehliar

ProAsic-plus PLL

I'm about to use an APA1000 with Actels implementation of dual port RAMs. These require the use of the PLL to create a...
1 comments posted 19yrs
posted by kev.parsons
1 comments posted 19yrs posted by kev.parsons