Field-Programmable Gate Arrays

DDR SDRAM controller for virtex 2 pro

I want to use a DDR SDRAM on my virtex 2 pro platform; however the vhdl controller available is for a 256Mb micron SDRA...

0 comments posted 19yrs

posted by ralstef

0 comments posted 19yrs posted by ralstef

read fpga

Can anybody tell me how to read the contents of the FPGA? I am working on xupv2p development board and after I download...

2 comments posted 19yrs

posted by nmichou

2 comments posted 19yrs posted by nmichou

EDK tri-state control

Hello, I am working with an unusual board that has two Xilinx Virtex 4 FX60's on it in a top/bottom mirrored configurat...

1 comments posted 19yrs

posted by jshamlet

1 comments posted 19yrs posted by jshamlet

Xilinx (without init value) has a constant value of 0?

I am constantly getting the following warnings when compiling in Xilinx: FF/Latch (without init value) has a constant v...

4 comments posted 19yrs

posted by ian.peikon

4 comments posted 19yrs posted by ian.peikon

Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?

The Spartan-3E datasheet indicates that the devices only support 2.5V differential output standards (LVDS and LVPECL),...

7 comments posted 19yrs

posted by LT1Z07

7 comments posted 19yrs posted by LT1Z07

Webpack 9.1 problems with Impact on parallel cable

After upgrading to Webpack 9.1 (and then directly to service pack 1) on a Windows XP machine connected to a Diligent Sp...

7 comments posted 19yrs

posted by jecel

7 comments posted 19yrs posted by jecel

Condition Variable in pthread.h

Hello, I have a Spartan 3E and I have implemented a Xilkernel and pthread for threading. Now I want to use "condition v...

0 comments posted 19yrs

posted by pbantunez

0 comments posted 19yrs posted by pbantunez

PCI Express user group

I know there is a PCI-Express newsgroup but there are very few posts of any relevance to PCI Express itself. Is there a...

4 comments posted 19yrs

posted by fred

4 comments posted 19yrs posted by fred

Altera DSP Builder

Hi guys, Seems like Altera's DSP Builder has undergo a lot of improvements over the past year or so. Trying to connect...

0 comments posted 19yrs

posted by d2clin

0 comments posted 19yrs posted by d2clin

Xc2v6000 package for ise

Hi , I am new to fpga and I am writing a program for my xilinx virtex 2 xc2v6000 chip. since my ISE software doesn't co...

1 comments posted 19yrs

posted by pcvijay30

1 comments posted 19yrs posted by pcvijay30

plb_gemac SerDes mode on V4-FX?

Hi, Can anyone confirm if the plb_gemac_v1_01_a in SerDes/MGT mode is supported on the V4-FX family? The datasheet (DS4...

0 comments posted 19yrs

posted by jwilliams

0 comments posted 19yrs posted by jwilliams

EDA course development

hello, first of all, i apologize for posting this in multiple groups. i recently start teaching at a university and i a...

1 comments posted 19yrs

posted by pallavgupta

1 comments posted 19yrs posted by pallavgupta

virtex4 configuration via XCF32P Prom

I'm confused about how to configure the FPGA via the platform flash XCF32P Prom. I have a JTAG serial chain that goes c...

3 comments posted 19yrs

posted by matt.fischler

3 comments posted 19yrs posted by matt.fischler

Question about simple design

Hello, I have the following VSD (very simple design) module a2v(clka, clkb); input clka; output clkb; buf b1(clkb,clka)...

3 comments posted 19yrs

posted by <carshie>

3 comments posted 19yrs posted by <carshie>

Where is help for schematic entry?

I can't find any help files about schematic entry, please advise?

2 comments posted 19yrs

posted by <carshie>

2 comments posted 19yrs posted by <carshie>