Field-Programmable Gate Arrays

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ProAsic-plus PLL

I'm about to use an APA1000 with Actels implementation of dual port RAMs. These require the use of the PLL to create a...
1 comments posted 19yrs
posted by kev.parsons
1 comments posted 19yrs posted by kev.parsons

DDR SDRAM controller for virtex 2 pro

I want to use a DDR SDRAM on my virtex 2 pro platform; however the vhdl controller available is for a 256Mb micron SDRA...
0 comments posted 19yrs
posted by ralstef
0 comments posted 19yrs posted by ralstef

read fpga

Can anybody tell me how to read the contents of the FPGA? I am working on xupv2p development board and after I download...
2 comments posted 19yrs
posted by nmichou
2 comments posted 19yrs posted by nmichou

EDK tri-state control

Hello, I am working with an unusual board that has two Xilinx Virtex 4 FX60's on it in a top/bottom mirrored configurat...
1 comments posted 19yrs
posted by jshamlet
1 comments posted 19yrs posted by jshamlet

Condition Variable in pthread.h

Hello, I have a Spartan 3E and I have implemented a Xilkernel and pthread for threading. Now I want to use "condition v...
0 comments posted 19yrs
posted by pbantunez
0 comments posted 19yrs posted by pbantunez

PCI Express user group

I know there is a PCI-Express newsgroup but there are very few posts of any relevance to PCI Express itself. Is there a...
4 comments posted 19yrs
posted by fred
4 comments posted 19yrs posted by fred

Altera DSP Builder

Hi guys, Seems like Altera's DSP Builder has undergo a lot of improvements over the past year or so. Trying to connect...
0 comments posted 19yrs
posted by d2clin
0 comments posted 19yrs posted by d2clin

Xc2v6000 package for ise

Hi , I am new to fpga and I am writing a program for my xilinx virtex 2 xc2v6000 chip. since my ISE software doesn't co...
1 comments posted 19yrs
posted by pcvijay30
1 comments posted 19yrs posted by pcvijay30

plb_gemac SerDes mode on V4-FX?

Hi, Can anyone confirm if the plb_gemac_v1_01_a in SerDes/MGT mode is supported on the V4-FX family? The datasheet (DS4...
0 comments posted 19yrs
posted by jwilliams
0 comments posted 19yrs posted by jwilliams

EDA course development

hello, first of all, i apologize for posting this in multiple groups. i recently start teaching at a university and i a...
1 comments posted 19yrs
posted by pallavgupta
1 comments posted 19yrs posted by pallavgupta

virtex4 configuration via XCF32P Prom

I'm confused about how to configure the FPGA via the platform flash XCF32P Prom. I have a JTAG serial chain that goes c...
3 comments posted 19yrs
posted by matt.fischler
3 comments posted 19yrs posted by matt.fischler

Question about simple design

Hello, I have the following VSD (very simple design) module a2v(clka, clkb); input clka; output clkb; buf b1(clkb,clka)...
3 comments posted 19yrs
posted by <carshie>
3 comments posted 19yrs posted by <carshie>