What chip exactly are you looking at, and what information do you want to know ?
I've looked in details at the virtex-2 XDL file format, and it's rather self-explanatory. You may want to read the chip's datasheets first to have a better grasp of the routing in the chips.
Basically, the wires all have names which are locally defined with respect to a specific CLB. The pips in the .XDL are connections between locally-named wires.
Let's take a simple example from a v2 chip:
net "yCoordMultAdd/lutfunc-E0" , outpin "yCoordMultAdd/lutfunc-E0" Y , inpin "yCoordMultAdd/carry" F3 , pip R28C45 Y0 -> OMUX3 , pip R29C46 F3_B0 -> F3_B_PINWIRE0 , pip R29C46 OMUX_SE3 -> F3_B0 , ;
The wire has a fanout of 1. It starts from R28C45 Y0, goes through the first pip to R28C45 OMUX3. This wire goes to the R29C46 CLB site, where its name becomes OMUX_SE3, then is driven to F3_B0 by the last pip (the middle pip is actually a pseudo-pip which has no hardware meaning).
As far as I know, there's no public document about the exact routing wires available on Xilinx chips, contrary to Altera. You can, however, derive such information from the xdl file, as Xilinx chips are pretty regularly layed out (contrary to Altera's there again).