Xilinx Interconnects/Routing

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I want to know it too.

This is a very complicated subject, with many hundred man-years of development behind it. Tell us: Why do you want to know, or why do you need to know? Peter Alfke, Xilinx

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I know It is way too complicated..... :-) I am working on partial reconfiguration ryte now....my prof wanted me to dig deep dwn into it......if I get to know abt the routing details, I may b able to work on different benchmark ckts....

Thank you pete.....

Mr.B

Hey Pete...

Could u plz tel me watz happening wid the XDL file....

Thanks in Advance

Mr.B

by

routing

You're so old skool, Peter.

JB

Hey all,

Lets not keep arguing abt the spellings and other stuffs in here. No offence JB!!!!!! Lets learn something. Anyways, I am sorry if I was disrespectful to anyone. Please let us know something about the routing details(If at all someone knew).

Mr.B

As I mentioned before, the routing structure is the result of over a thousand man-years of development effort, not something that is easily explained on a newsgroup. But the real question had to do with partial reconfiguration, and I will dig up a few references to that. Peter ==============

Hello,

What chip exactly are you looking at, and what information do you want to know ?

I've looked in details at the virtex-2 XDL file format, and it's rather self-explanatory. You may want to read the chip's datasheets first to have a better grasp of the routing in the chips.

Basically, the wires all have names which are locally defined with respect to a specific CLB. The pips in the .XDL are connections between locally-named wires.

Let's take a simple example from a v2 chip:

net "yCoordMultAdd/lutfunc-E0" , outpin "yCoordMultAdd/lutfunc-E0" Y , inpin "yCoordMultAdd/carry" F3 , pip R28C45 Y0 -> OMUX3 , pip R29C46 F3_B0 -> F3_B_PINWIRE0 , pip R29C46 OMUX_SE3 -> F3_B0 , ;

The wire has a fanout of 1. It starts from R28C45 Y0, goes through the first pip to R28C45 OMUX3. This wire goes to the R29C46 CLB site, where its name becomes OMUX_SE3, then is driven to F3_B0 by the last pip (the middle pip is actually a pseudo-pip which has no hardware meaning).

As far as I know, there's no public document about the exact routing wires available on Xilinx chips, contrary to Altera. You can, however, derive such information from the xdl file, as Xilinx chips are pretty regularly layed out (contrary to Altera's there again).

JB

thanks a lot folks......

Mr.B