query in P&R of FPGA

I am using cyclone 2 device with quartus 6.0 software.

I don't know about anyone else, but I don't have a clue what you are talking about, or how you expect anyone to be able to help you with such a lack of information.

Regards,

ram,

Have you looked at this part of the Quartus manual yet:

It describes a way to partition your design so that the parts that do not change also do not need to be re-synthesized or re-P&Red.

Also, have you properly constrained your design? (i.e. clock constraints on clock pins, Tsu, Tco etc on the I/O pins etc etc?) If Quartus does not know what to aim for, it won't try, in order not to waste excessive electricity.

First, read the abovementioned documentation (aka RTFM). Second, read some more documentation on design constraints. Third, check your constraints. Fourth, post detailed questions to comp.arch.fpga, including bits of sample code, concrete results of what happens when you change what etc etc

Best regards,

Ben

I bet 100 bucks that your design either contains asynchronous logic (gated clocks, ripple clocks) or doesn't meet timing. If design is asynchronous then it's your prob. If it violates timing you should get information from timing analyzer. There is no need to get angry on the Altera guys. Check your design first.

Cheers, Phil