I am a doing design.I am emulating FPGA.My problem is whenever i change one line of code(verilog) on top model i am getting getting most worst result.How to preserve the previous information.My time is wasting really like hell.I dont know how to end this design also.But functionally i proved the design is working.due to P& R result is changing.Really i am getting anger on the altera guys.Can you suggest me a solution
- posted
17 years ago