or1k on spartan 3, 400K gate version

^^^^^^^^^^

You are truly using an obscene amount of LUTs as RAM in this design if I my say so. My guess is that you are implementing the caches in distram instead of blockrams. As a comparison, here is a breakdown of an OR1200 design that we are using:

+-----------------------------+--------+--------+--------+-----------+--------+--------+ | Module | LUTS | FF | RAMB16 | MULT18x18 | IOB | DCM | +-----------------------------+--------+--------+--------+-----------+--------+--------+ | cpu | 1 | | | | | | | cpu/dwb_biu | 12 | 72 | | | | | | cpu/iwb_biu | 66 | 74 | | | | | | cpu/or1200_cpu | 3824 | 837 | 2 | 4 | | | | cpu/or1200_dc_top | 235 | 40 | 5 | | | | | cpu/or1200_ic_top | 186 | 38 | 5 | | | | | cpu/or1200_immu_top | 11 | 33 | | | | | | cpu/or1200_pic | 27 | 38 | | | | | | cpu/or1200_sb | 309 | 352 | | | | | | cpu/or1200_tt | 170 | 96 | | | | | ... lots of other modules not part of the or1200 ... +-----------------------------+--------+--------+--------+-----------+--------+--------+ | Total | 9499 | 4402 | 28 | 4 | 115 | 2 | +-----------------------------+--------+--------+--------+-----------+--------+--------+

This is targetted at a Virtex 2-4000 but the LUT/FF count should be similar when targetted to another FPGA with 4 input LUTs and blockrams. For the curious, the opencores ethernet controller is responsible for most of the rest of the LUT/FF usage.

/Andreas

I just realized that this answer might not have been extremely helpful. Take a look at the or1200_defines.v file if you haven't already done so. Specifically, search for XILINX and you should be able to configure the memory type you are using.

/Andreas

I thought it explained things pretty well. The synthesis tools normally do a good job of inferring BlockRAM. However, if you code so that, for example, there's an asynchronous read, the tool has no choice but to use distram. HTH, Syms.

CMOS, Hi,

I'm currently fooling with LatticeMico32 [1] on the Spartan3E Starter Kit (Spartan3E-500, ~10 kLUTs). LM32 takes < 1500 LUTs, is under GPL and there is a GCC port. Even though I don't have much experience with that CPU, it looks quite good.

Before that I used LEON3 [2] -- It takes ~5000 LUTs on that chip (without caches), reaches only 50MHz but is fully SPARC v8 compatible.

j.

[1] mico32/index.cfm [2]

hi,

thak you very much for all the information. im gonna have a look at both of the recomondations.

CMOS

I'm playing with Plasma - most MIPS I(TM) opcodes

It fit in a spartan3 XC3S200 the author provides a cross gcc compiler for windows or You can recompile (as me) a cross gcc for linux

Sandro