question abt DPRAM

Hi,

I have an DPRAM which has writes taking place at a certain freq on port A (100 Mhz) & reads with a gated clock which is derived from the

Thanks in advance

Sorry had to repost it.There is a correction . The enable signal for the clock does not follow a uniform pattern

That makes all the difference.

How about this: an LVCMOS output stage drives a 48MHz signal over a 12-inch stretch of FR4 terminated with a 10K resistor to Vcc and a 100pF capacitor to Gnd. What colour is the PCB?

-Ben-

You driving a bus with three signal. At the first connector, 2 get off, but

HTH, Syms.

Sym> You driving a bus with three signal. At the first connector, 2 get off ...

Sheesh, How can this guy learn with examples like that? Try this:

My teammate and I run a race. He runs the mile 5 seconds faster than I do. What size hat should I buy?

If I understand your problem correctly, you have data coming in faster that it is going out. To answer your question, I need to know how long the DPRAM will be running.

No dpram depth can handle such situation without losing the data when incoming sustain rate is faster than its going out, don't read other guys posts, they seem having a party going on :)). Anyway can you tell more about how your in/out data behave?

How many incoming bytes are there, per

Same question for out going data. When you answer these two questions you would also figure out the requirement depth

Red, obviously, unless there is a full moon.