Hi, I am creating an FPGA (Spartan 3 XCS400) based replacement for one of our old board designs which uses IDT 7201 -
Initially I cheated a little and created a clock for the FIFOs and lined up my stimulus to that clock and worked out the bugs in my design.
To actually match the original board however I need to work without a clock - the board I am replacing is controlled by another board with a
32MHz clock on it but that clock does not pass down the backplane to my board so all I have are various signals that I must act on.
Most of the design seems to work fine except for a limitation in the FIFO core (I am using the Xilinx async FIFO core v6.1) - it must get few clocks from each domain after a reset otherwise it will not accept writes (or reads presumably but it's hard to tell).
I did put a 50MHz clock on my board Just In Case(tm) however, obviously, it won't be synchronised with the clock on the main card so I need to sync up the incoming reset signal and then count out a few clocks to the FIFO core.
I'm still working on the last part trying to get it working but since my design reads like a "How not to use an FPGA" (through no fault of my own! :) plus I am normally a software guy, it's hard going.
Has anyone done this sort of thing before? (and would be willing to share their solution).
I am also considering taking the 50MHz clock on my board and multiplying it up to, say, 150MHz and sychronising/one-shotting all of the signals from the other board to that.