Field-Programmable Gate Arrays

Questions about pci transactions in my core

I wrote pci core and implemented it on a virtex 4 fpga, the pci core served as a slave. Now the config space can be rea...

2 comments posted 19yrs

posted by lipeng.net

2 comments posted 19yrs posted by lipeng.net

Compile uCLinux for Spartan 3e

Does anyone Know how can I compile uClinux-dist for Spartan 3E. I have done the next: download uClinux-dist download uC...

5 comments posted 19yrs

posted by pbantunez

5 comments posted 19yrs posted by pbantunez

Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.

Hi All, Hopefully this is a simple fix... I complied Xilinx simulation libraries with COMPXLIB... and it seemed to work...

3 comments posted 19yrs

posted by tony.uniquify

3 comments posted 19yrs posted by tony.uniquify

Spartan-3E starter kit : trouble with configuration from NOR Flash

Hi, I have recently purchased the Spartan-3E starter kit and I am having trouble to configure the FPGA with what is in...

4 comments posted 19yrs

posted by engr.saqib.riaz

4 comments posted 19yrs posted by engr.saqib.riaz

Multiple MicroBlaze based Multiprocessor system

Hello All, Is it possible to instantiate multiple MicroBlaze through Base System Builder in anyways, The tutorial says...

2 comments posted 19yrs

posted by shantchandrakar

2 comments posted 19yrs posted by shantchandrakar

Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?

HI All, I am confused. I have the free version of ISE 9.1 >From what I understand, the free version limits me to the lo...

4 comments posted 19yrs

posted by tony.uniquify

4 comments posted 19yrs posted by tony.uniquify

For Sale: 234 pieces Philips / Xilinx P3Z22V10-BA Zero-Power PLD

Apologies for this advert; I hope somebody finds them useful. I don't like chucking out something which is potentially...

3 comments posted 19yrs

posted by nospam

3 comments posted 19yrs posted by nospam

ANNC: FPGA Video Interfacing Fundamentals Webcast

Lattice is holding a webcast tomorrow Wednesday, February 7, "FPGA Video Interfacing Fundamentals." The presenter will...

0 comments posted 19yrs

posted by bart.borosky

0 comments posted 19yrs posted by bart.borosky

regarding the usage of embedded ethernet MAC on Virtex4

Hi all, I started working on interfacing PC with Virtex4 FPGA through Ethernet Embedded MAC which is there on Virtex4 F...

0 comments posted 19yrs

posted by bachimanchi

0 comments posted 19yrs posted by bachimanchi

generating VHDL code from Matlab code for DSP - wavelet image compression

Is there a way of generating VHDL code from Matlab code for DSP, more precisely image processing using wavelet transfor...

8 comments posted 19yrs

posted by maricic

8 comments posted 19yrs posted by maricic

Xilinx Virtex5 board

Hi, We are trying to implemnt a very huge design. For that we need a v5lx330 fpga. Also we need video in/out, AD/DA con...

3 comments posted 19yrs

posted by vssumesh_asic

3 comments posted 19yrs posted by vssumesh_asic

HI guys...about EDK

Hey guys, is there anyone who uses Virtex2p with compact flash card as Inst Mem and DDR as data mem?..I am a newbie for...

0 comments posted 19yrs

posted by angeloaj

0 comments posted 19yrs posted by angeloaj

[Q]: Is Digilent still in business ???

Hi !! I sent an inquiry about 3 weeks before to digilent, but neither an answer, nor a reply yet. Same for the 2nd & 3rd...

6 comments posted 19yrs

posted by ChaosKosta

6 comments posted 19yrs posted by ChaosKosta

CFP; deadline extended

Paper submission deadline is extended. The 2007 International Conference on High Performance Computing, Networking, and...

0 comments posted 19yrs

posted by jeedward

0 comments posted 19yrs posted by jeedward

moving data from slower to faster clock domain

Hi, what is the best way of moving data from a faster clock domain (100 mhz ) to slower one(75 Mhz)? thanks

3 comments posted 19yrs

posted by bajajk

3 comments posted 19yrs posted by bajajk