Hi,
I'm trying to fix the location of some primitive cells (apex20ke_lcell) in a post-synthesis netlist for an Altera APEX20KE FPGA.
I have synthesized (quartus_map) and placed&routed (quartus_map) my Verilog HDL design using Quartus II. Then I have created a Verilog Quartus Mapping File (VQM), which contains the instantiated primitive cells of the device and I have back-annotated the location constraints into the Quartus settings file (QSF).
In the QSF, there are a lot of location constraints, a la set_instance_assignment -name LL_NODE_LOCATION LC3_13_J4 -to "HDAND2D1:inv_i_10|Z~116_B" -section_id aes_sbox_canright
When I use the VQM and QSF file for a new fitting attempt, I get warnings for each location constraint like Warning: Node "HDAND2D1:inv_i_10|Z~116_B" is assigned to location or region, but does not exist in design
Either I'm doing something terribly wrong or Quartus isn't able to understand its own back-annotation.
I hope that somebody can shed some light on this.
Regards,
Stefan Tillich